Wafer-Level TSV Testing via Test Conductive Layer
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Solution Overview
Problem
The existing methods for testing through-silicon vias (TSVs) in semiconductor apparatuses are inefficient as they are typically performed after packaging, leading to increased fabrication costs due to the need for unnecessary redundancy TSVs and discarded packages when fail rates exceed prepared redundancy.
Innovation Solution
A test method that involves forming a test conductive layer around the TSV, applying different voltages to the TSV and a conductive layer, measuring the voltage difference, and determining TSV failures before grinding the substrate, allowing for identification and potential repair of faulty TSVs at the wafer level before packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If TSV testing is performed after packaging, then the testing process is simple, but fabrication costs increase due to unnecessary redundancy TSVs and discarded packages
Solution Approach 1:
The patent applies preliminary action by performing TSV testing at the wafer level before packaging. Test conductors are formed on the wafer surface to provide access to TSV endpoints, enabling testing to be conducted on the entire wafer rather than after individual packaging. This early detection allows faulty TSVs to be identified and repaired before final packaging, reducing waste and fabrication costs.
Solution Approach 2:
The patent segments the testing process by separating TSV testing from the final packaged product testing. By implementing wafer-level testing with dedicated test conductors, the testing function is separated into an independent stage that can be performed on the wafer before dicing and packaging, enabling more efficient fault detection and repair.
2Reliability
If redundancy TSVs are prepared for potential failures, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent enables precise identification of faulty TSVs through wafer-level testing with test conductors, allowing repairs to be performed only on specific failed TSVs rather than requiring redundancy for all TSVs. This targeted approach maintains reliability by fixing actual failures while avoiding the complexity of universal redundancy structures.
3Productivity
If wafer-level testing is implemented, then productivity is improved by reducing waste, but device complexity increases due to additional test conductors
Solution Approach 1:
The patent segments the conductor functions by creating separate test conductors distinct from signal conductors. Test conductors are specifically designed to access TSV endpoints for testing purposes, while signal conductors handle operational signals. This segmentation enables independent testing functionality without interfering with the primary device operation.
Solution Approach 2:
The test conductors serve multiple functions: they provide electrical access to TSV endpoints for resistance testing, and can potentially serve as additional signal paths or interconnects in the final device. This multi-functionality reduces the net increase in device complexity while enabling comprehensive wafer-level testing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs by identifying and potentially repairing faulty TSVs before packaging, minimizing the need for redundancy and discarding entire memory packages.
Implementation Method 1
the TSV and the peripheral structure thereof may form a MOS capacitor structure, which includes the TSV made of a conductive material, the insulating layer, and the silicon substrate
Data Source
AI summary
A test method of a semiconductor apparatus before a wafer is ground may include applying voltages to a bump electrically coupled to a through-silicon via (TSV) which is buried in the wafer and a first conductive layer formed to be electrically connected to a rear surface of the TSV, wherein the first conductive layer is withdrawn into an upper surface of the wafer. The method may include measuring a voltage between the bump and the first conductive layer. The method may include comparing the measured voltage to a preset reference voltage. The method may include determining the TSV as a normal TSV in which no fail occurs, according a comparing result, and grinding the wafer to expose the rear surface of the TSV.