Tunable CMOS Template Matching for Low-Power Neural Spike Sorting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current neural spike recording systems face challenges in achieving real-time spike sorting with low power dissipation and small area footprint, particularly in categorizing neural spikes in-vivo, and implementing hardware fuzzy logic with minimal power and area constraints.
Innovation Solution
A tunable CMOS circuit with a memristor-based load is used to determine exact matches between analogue input signals and pre-set switch points, integrated into a template matching module for spike sorting, and a fuzzy logic gate with memristor-CMOS hybrid architecture for flexible and low-power fuzzy logic implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If fully digital or conventional analogue techniques are used for spike detection, then detection functionality is achieved, but power dissipation and area footprint increase due to expensive operational amplifiers and analogue multiplier blocks
Solution Approach 1:
The patent extracts and eliminates expensive operational amplifier and analogue multiplier blocks from the spike detection architecture. By using a simplified circuit topology that relies on passive RC filtering and direct comparator-based detection, the design removes unnecessary active components that consume power, while maintaining detection functionality through the essential switch point comparison mechanism
Solution Approach 2:
The patent employs inexpensive, simple CMOS switches and passive RC components instead of expensive operational amplifiers. The design uses basic transistor switches that can be rapidly fabricated in standard CMOS processes, replacing costly specialised analogue components with readily available, low-cost standard cells that achieve the same detection function with minimal power consumption
2Reliability
If conventional spike detection methods are used, then spike detection is achieved, but area footprint increases due to expensive operational amplifiers and analogue multiplier blocks
Solution Approach 1:
The patent removes large-area operational amplifier and analogue multiplier blocks from the circuit architecture. By using a compact comparator-based detection scheme with simple RC filtering, the design achieves spike detection functionality in a minimal area, eliminating the need for extensive analogue processing circuitry that would occupy valuable chip real estate
Solution Approach 2:
The patent uses a replicated, simplified detection unit that can be easily copied and tiled across the chip for multi-channel recording. The basic detection cell consisting of RC filters and comparators is designed to be compact and easily replicable, allowing parallel processing of multiple neural channels without proportionally increasing total area
3Productivity
If existing spike sorting architectures are used, then spike detection is achieved, but real-time categorization capability is insufficient
Solution Approach 1:
The patent performs preliminary spike detection and switch point identification using simple RC filtering and threshold comparison before attempting categorization. By pre-processing the neural signal to identify candidate spike events and their characteristic switch points, the system reduces the complexity of subsequent sorting operations, enabling real-time categorization without requiring complex post-processing algorithms
Solution Approach 2:
The patent implements dynamic, adaptive switch point adjustment that allows the detection system to adapt to varying neural signal characteristics in real-time. The switch points are not fixed but can be dynamically adjusted based on incoming signal statistics, enabling the system to maintain high detection accuracy across different recording conditions without requiring complex reconfiguration
Data Source
AI summary
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate, a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.