Tunnel Transistor Vertical Band-to-Band Tunneling Structure
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Solution Overview
Problem
Conventional transistors face limitations in reducing power consumption due to high leakage current and voltage swing, with tunnel transistors offering potential but struggling with low ON currents and small tunneling areas.
Innovation Solution
The fabrication of integrated circuits with tunnel transistors featuring vertically aligned source/drain regions and a gate structure beside the channel, allowing for increased band-to-band tunneling area and improved subthreshold swing, resulting in higher ON state current and lower OFF state leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lateral tunneling approach is used in tunnel transistors, then the structure is simpler to fabricate, but the ON current is relatively low due to small tunneling area
Solution Approach 1:
The patent transitions from lateral tunneling (2D planar structure) to vertical band-to-band tunneling (3D vertical structure). The tunnel transistor includes a source region, drain region, and channel region arranged vertically, with the gate electrode wrapping around the channel to create a vertical electric field that enables band-to-band tunneling. This dimensional change increases the effective tunneling area while maintaining fabrication feasibility through standard semiconductor processing techniques.
2Ease of manufacture
If conventional MOSFETs are used, then the device is easier to manufacture, but the subthreshold slope is fundamentally limited to 60 mV/decade at room temperature
Solution Approach 1:
The patent changes the fundamental operating mechanism of the transistor from conventional drift-diffusion transport to quantum mechanical band-to-band tunneling. By designing the source and drain regions with appropriate doping concentrations and the channel with a narrow width, the patent enables direct band-to-band tunneling under the gate, which allows the subthreshold slope to overcome the 60 mV/decade limit imposed on conventional MOSFETs by thermal effects.
3Power
If vertical band-to-band tunneling approach is used, then the tunneling area is large providing high ON current, but the fabrication process becomes more complex
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions: a heavily doped source region, a narrow channel region, and a heavily doped drain region, all arranged vertically. The gate electrode is segmented into multiple portions that wrap around the channel at different heights. This segmentation allows each region to be optimized for its specific function while maintaining overall fabrication feasibility through standard semiconductor processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power efficiency by increasing ON state current and reducing OFF state leakage, leading to lower power consumption and a smaller transistor footprint.
Implementation Method 1
tunnel transistors using a vertical band-to-band tunneling ('BTBT') approach, similar to the gate induced drain leakage ('GIDL') mechanism present in conventional MOSFETs
Implementation Method 2
epitaxially growing a pocket region of semiconductor material on the vertical side surface of the fin structure and on the exposed horizontal surface of the semiconductor material
Data Source
AI summary
Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.