Tunneling Junction LED Structure for Micro-Display Light Output
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Solution Overview
Problem
Existing light emitting diodes (LEDs) face challenges in enhancing light output efficiency, particularly when applied to micro-scale or nano-scale display devices, due to limitations in semiconductor layer configurations and doping concentrations.
Innovation Solution
The proposed light emitting element incorporates a tunneling junction layer with specific semiconductor layer thicknesses and doping concentrations, positioning the active layer adjacent to the intermediate portion, and is surrounded by an insulating layer to enhance light emission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor layer configurations are used in micro-scale LEDs, then device size is reduced, but light output efficiency deteriorates
Solution Approach 1:
The patent applies local quality by creating asymmetric semiconductor layer thicknesses on opposite sides of the active layer. Specifically, the first semiconductor layer has a different thickness than the second semiconductor layer, with the thicker side positioned to optimize light extraction. This local variation in thickness allows the micro-scale LED to maintain efficient light output by enhancing light extraction at critical locations while keeping the overall device size reduced.
Solution Approach 2:
The patent employs parameter changes by systematically varying the thickness parameters of the semiconductor layers. The first semiconductor layer is configured with a thickness in the range of 10-50 nm, while the second semiconductor layer has a thickness of 50-100 nm. By optimizing these thickness parameters, the patent achieves improved light output efficiency in micro-scale LEDs without requiring conventional larger dimensions.
2Length of moving object
If semiconductor layer thicknesses are reduced for miniaturization, then device size decreases, but light emission performance worsens
Solution Approach 1:
The patent applies asymmetry by deliberately making the first and second semiconductor layers have different thicknesses. The first semiconductor layer (10-50 nm) is thinner than the second semiconductor layer (50-100 nm). This asymmetric configuration optimizes the balance between electron injection and light extraction processes, allowing miniaturization while maintaining or enhancing light emission performance compared to symmetric conventional designs.
3Ease of manufacture
If uniform doping concentrations are used, then manufacturing is simplified, but light output efficiency is limited
Solution Approach 1:
The patent applies local quality by implementing non-uniform doping concentrations in different semiconductor layers. The first semiconductor layer is doped with a first doping concentration, while the second semiconductor layer is doped with a second doping concentration that differs from the first. This localized variation in doping optimizes carrier injection and recombination processes in each layer, thereby enhancing overall light output efficiency while maintaining manufacturing feasibility through controlled doping processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves light output efficiency by optimizing semiconductor layer thicknesses and doping concentrations, enhancing the performance of LEDs in micro-scale or nano-scale display devices.
Implementation Method 1
a third semiconductor layer including a third-first semiconductor layer and a third-second semiconductor layer stacked on the second semiconductor layer; and a fourth semiconductor layer disposed on the third-second semiconductor layer. The third semiconductor layer may be a tunneling junction layer.
Data Source
AI summary
A light emitting element includes: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; a third semiconductor layer comprising a third-first semiconductor layer and a third-second semiconductor layer stacked on the second semiconductor layer; and a fourth semiconductor layer disposed on the third-second semiconductor layer. The third semiconductor layer is a tunneling junction layer. A sum of a thickness of the fourth semiconductor layer and the third-second semiconductor layer is different from a sum of a thickness of the second semiconductor layer and the third-first semiconductor layer.