Turbo Decoder Parity Soft Output for Equalization Feedback
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Solution Overview
Problem
Conventional turbo decoders do not provide soft output values for parity bits, which are essential for advanced receiver techniques in digital communication systems, particularly in wireless communications, limiting their capability to perform turbo equalization and interference cancellation.
Innovation Solution
A system and method that generate revised parity bit soft information (LLR values) using input and output signals from a turbo decoder, incorporating a parity bit soft information generation circuit to determine initial forward and backward metrics and branch metrics, enabling the calculation of output parity bit soft information values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional turbo decoder implementation is used, then the decoder complexity is reduced and operation is simplified, but soft output information for parity bits is not provided, limiting advanced receiver techniques
Solution Approach 1:
The decoder is segmented into distinct functional blocks: a conventional turbo decoder block that processes systematic bits, and a separate parity bit soft information generation block that computes LLR values for parity bits. This segmentation allows the main turbo decoder to remain simple while adding parity bit processing capability through a dedicated module that takes turbo decoder outputs and generates the required soft information for feedback.
2Reliability
If turbo equalization and interference cancellation are implemented, then receiver performance is improved, but soft output information for both systematic and parity bits is required, increasing decoder complexity
Solution Approach 1:
An intermediary parity bit soft information generation block is introduced between the conventional turbo decoder and the feedback mechanism. This intermediary takes the systematic bit LLR outputs from the turbo decoder, combines them with stored input parity bit soft information, and generates the required output parity bit soft information. This approach enables advanced receiver techniques without requiring fundamental changes to the core turbo decoder architecture.
3Adaptability or versatility
If only input LLR values and fed back systematic soft output are used, then the decoding operation is simplified, but the capability to provide soft output for parity bits is lost
Solution Approach 1:
The system performs preliminary action by storing the input parity bit soft information (LLR values) before the turbo decoding operation. This stored information is then retrieved and combined with the turbo decoder outputs in the parity bit soft information generation block. By preparing and storing the necessary input data in advance, the system enables comprehensive soft output generation without adding complex real-time processing requirements during the main decoding operation.
Data Source
AI summary
A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.