Twin-Bit Trench Floating-Gate Memory Cell for Higher Density
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Solution Overview
Problem
Current non-volatile memory devices face challenges in further reducing the size of memory cells to increase the number of cells that can be formed in a given substrate area, particularly in configurations with buried floating gates and trenches.
Innovation Solution
A twin bit memory cell design is implemented, featuring two separate trenches with two floating gates each, a continuous channel region extending from one source region to another, and controlled by erase and word line gates, eliminating the need for a separate drain region and reducing cell height and lateral dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a linear channel region extending along the substrate surface is used, then the channel conductivity can be effectively controlled, but the memory cell occupies larger surface area
Solution Approach 1:
The channel region is folded back into the substrate, transitioning from a linear surface extension to a three-dimensional path that extends along sidewalls and through the substrate depth. This dimensional change allows the channel to maintain sufficient length for conductivity control while reducing the lateral surface footprint of the memory cell.
Solution Approach 2:
The channel region is nested within the substrate structure by extending it along the sidewalls of trenches and through the substrate depth. This nesting approach allows the channel to be contained within the vertical profile of the memory cell rather than extending horizontally, thereby reducing surface area occupation.
2Quantity of substance
If separate drain regions are included for each memory cell, then the channel conductivity can be fully controlled, but the number of memory cells per surface area unit decreases
Solution Approach 1:
Adjacent memory cells share common source and drain regions formed in the substrate. By merging these regions between neighboring cells, the patent eliminates redundant structures and increases the density of memory cells that can be packed into a given surface area while maintaining full channel conductivity control through the shared regions.
Solution Approach 2:
The shared source and drain regions serve multiple adjacent memory cells simultaneously, making these regions universal structures that perform the same function for multiple cells. This multi-functionality reduces the overall device complexity and increases cell density without compromising individual cell operation.
3Length of moving object
If the channel region extends linearly along the substrate surface, then the channel length is sufficient for conductivity control, but the cell height and lateral dimensions increase
Solution Approach 1:
The channel region transitions from a two-dimensional surface extension to a three-dimensional path that utilizes the vertical depth of the substrate. By extending the channel along sidewalls and through the substrate thickness, the patent achieves sufficient channel length without increasing lateral dimensions, effectively using the third dimension to resolve the length conflict.
Solution Approach 2:
The channel region follows a curved or folded path through the substrate rather than a straight line, utilizing the available three-dimensional space efficiently. This curved configuration allows the channel to achieve adequate length while maintaining compact lateral dimensions by navigating through the vertical profile of the memory cell structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves miniaturization of memory cells by utilizing trenches for floating gates, enhancing programming efficiency through hot electron injection and reducing cell size without the need for additional drain regions, thereby increasing memory density.
Implementation Method 1
This design enhances programming efficiency through hot electron injection
Implementation Method 2
using a word line gate to control conductivity
Implementation Method 3
a first erase gate of conductive material disposed over and insulated from the first floating gate, a second erase gate of conductive material disposed over and insulated from the second floating gate
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.