Two-bit SOT MRAM Cell with Series MTJs for High Density
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Solution Overview
Problem
Conventional two-terminal MRAM devices face limitations such as low bit density, oxide reliability issues, and high write power, while attempts to increase bit density through shared heavy metal or stacked MTJs with different torque mechanisms either fail to program MTJs independently or retain limitations like tunnel barrier reliability and high write energy.
Innovation Solution
A two-bit SOT MRAM cell using three transistors with two MTJs in series, sharing a reference layer, allows independent programming of each bit by passing current through separate heavy metal layers, decoupling write paths and enhancing speed and energy efficiency compared to STT-based cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional two-terminal MRAM devices are used, then the structure is simple, but the bit density is low and write power is high
Solution Approach 1:
The patent divides a single MTJ into two separate MTJs (first MTJ and second MTJ) with different areas within the same memory cell. This segmentation allows each MTJ to represent one bit, enabling 2-bit storage per cell and improving bit density while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent introduces area dimensionality as a key differentiator between the two MTJs in series. By making the first MTJ have a larger area than the second MTJ, the patent creates distinguishable resistance states for 2-bit storage, effectively using spatial dimension (area) to encode additional information beyond what a single MTJ can provide.
2Quantity of substance
If shared heavy metal or stacked MTJs with different torque mechanisms are used to increase bit density, then bit density improves, but independent programming of MTJs fails or tunnel barrier reliability issues persist
Solution Approach 1:
The patent applies local quality by giving each MTJ a distinct area (first MTJ has larger area, second MTJ has smaller area) while maintaining the same stack structure and materials. This local differentiation in area allows independent identification and programming of each MTJ through resistance measurements, ensuring reliable 2-bit storage without the complexity of different torque mechanisms.
3Quantity of substance
If two MTJs with different areas are used in series, then bit density increases and independent programming is enabled, but device complexity increases
Solution Approach 1:
The patent uses a universal MTJ stack structure for both the first and second MTJs, maintaining the same materials and layer configuration. This multi-functionality approach allows the same structural template to serve dual purposes (storing two bits) while minimizing the increase in device complexity. The only differentiation needed is in the area dimension, which can be achieved through straightforward fabrication process adjustments.
4Ease of operation
If conventional MRAM reading is used, then the process is simple, but reading and writing speeds are limited and energy consumption is high
Solution Approach 1:
The patent enables dynamic and selective programming of individual MTJs within the series connection. By controlling which MTJ (first or second) receives write current through selective transistor activation, the system achieves faster write operations without affecting the other bit. Similarly, read operations can selectively measure resistance states, improving overall operation speed while maintaining relative simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster writing and reading speeds, improved bit density, and reduced energy consumption by allowing independent programming of each bit, resulting in approximately 2-3 times faster reading and significant time savings during writing compared to traditional MRAM cells.
Implementation Method 1
The first MTJ is coupled to a first heavy metal layer... selectively activating one or more of the first, second, and third transistors to cause current to flow through a heavy metal layer that is associated with the particular MTJ
Implementation Method 2
MRAM stores the data in magnetic domains using magnetic storage elements. The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization... determining a resistance of the MRAM cell... determining a two-bit value of the MRAM cell based on the determined resistance
Data Source
AI summary
Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.