Two-NMOS Ring Oscillator Inverter for Low Supply Sensitivity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ring oscillators are highly sensitive to supply voltage fluctuations and temperature variations, leading to increased power consumption and instability in systems like phase-locked loops.
Innovation Solution
Inverters based on NMOS transistors with specific circuitry for bias voltage control and capacitance tuning, along with temperature-compensated bias voltage generation, reduce supply sensitivity and stabilize oscillation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If high PSRR LDOs and active current sources are added to reject supply noise, then supply voltage rejection is improved, but minimum supply voltage requirements increase and power consumption increases
Solution Approach 1:
The patent extracts and removes the high PSRR LDO and active current source circuitry from the system. Instead of using these complex noise rejection components, the invention uses a simplified inverter design with two NMOS transistors that inherently achieves low supply sensitivity without requiring additional power-hungry regulation circuitry.
Solution Approach 2:
The patent replaces expensive, complex high PSRR regulation circuitry with a simple, low-cost inverter design using basic NMOS transistors. This simpler design achieves the same noise rejection function without the overhead of sophisticated power regulation components.
2Object-affected harmful factors
If high PSRR LDOs and active current sources are added to reject supply noise, then supply voltage rejection is improved, but minimum supply voltage requirements increase
Solution Approach 1:
The patent removes the high PSRR LDO circuitry that would otherwise be required to achieve good supply noise rejection. The simplified inverter design using two NMOS transistors achieves low supply sensitivity inherently, eliminating the need for additional voltage regulation stages that would raise the minimum supply voltage requirement.
Solution Approach 2:
Instead of adding complex regulation circuitry on top of a conventional inverter to achieve low supply sensitivity, the patent inverts the approach by designing the inverter itself with a novel two-NMOS structure that inherently provides low supply sensitivity, eliminating the need for additional regulation stages.
3Device complexity
If conventional ring oscillator design is used, then circuit simplicity is maintained, but temperature sensitivity increases causing PLL to go out of lock
Solution Approach 1:
The patent applies local quality by making the inverter stage itself temperature-compensated through the specific two-NMOS transistor configuration. Rather than adding global temperature compensation circuitry to a conventional oscillator, the temperature stability is built into the local inverter structure, maintaining overall circuit simplicity while improving reliability.
4Device complexity
If conventional inverter design is used, then design simplicity is maintained, but delay sensitivity to supply voltage increases
Solution Approach 1:
The patent inverts the conventional inverter design by using two NMOS transistors instead of the traditional NMOS-PMOS configuration. This inverted structure with the second NMOS transistor connected to the drain of the first creates a circuit that is inherently less sensitive to supply voltage variations, reducing delay sensitivity while keeping the design simple.
Data Source
AI summary
An inverter and a ring oscillator comprising a plurality of the inverters arranged in a ring is disclosed. Each inverter comprises an inverter input and an inverter output, wherein the inverter output of each inverter in the ring is coupled to the inverter input of the respective next inverter in the ring. At least one of the plurality of inverters comprises: a first NMOS transistor, comprising a first gate terminal coupled to the respective inverter input, a first drain terminal coupled to the respective inverter output, and a first source terminal; and a second NMOS transistor, comprising a second gate terminal, a second drain terminal and a second source terminal, wherein said second source terminal is coupled to said first drain terminal.