Two-Stage A/D Converter Using Residue Bits to Cut Circuit Complexity
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Solution Overview
Problem
Existing A/D converters for image sensors face challenges in achieving high resolution while minimizing noise and circuit complexity, particularly in requiring high amplifier gain and complex circuit structures for accurate conversion, especially when using serial-parallel converters.
Innovation Solution
The proposed A/D converter employs a two-stage architecture with a first cyclic A/D converter generating upper N bits and a second A/D converter generating lower M bits, where the first stage performs cyclic A/D conversion to reduce the accuracy requirements for the second stage, allowing for a simpler and more efficient circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-gain amplifier is used to reduce noise and achieve high resolution in A/D conversion, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The A/D converter is divided into two independent stages: a first-stage cyclic A/D converter that processes the upper bits (N bits) and a second-stage A/D converter that processes the lower bits (M bits). This segmentation allows each stage to be optimized independently, with the first stage handling the majority of the conversion complexity through cyclic modulation while the second stage can use a simpler architecture, thereby achieving high overall resolution without requiring a single complex high-gain amplifier system
Solution Approach 2:
The patent introduces a residue signal as an intermediary between the two conversion stages. The first-stage cyclic A/D converter outputs both upper-bit digital values and a residue analog signal, which then serves as the input to the second-stage A/D converter. This intermediary residue signal enables the division of the conversion task and allows the use of a simpler second-stage converter while maintaining high overall precision
2Measurement precision
If a serial-parallel A/D converter is used to achieve high resolution, then the measurement precision is improved, but the productivity decreases
Solution Approach 1:
The conversion process is segmented into two parallel-capable stages. The first-stage cyclic A/D converter can operate independently to generate upper-bit values, and the second-stage A/D converter can independently process the residue signal to generate lower-bit values. This segmentation enables potential parallel operation or pipelining, significantly improving conversion speed compared to traditional serial-parallel architectures that require sequential processing
Solution Approach 2:
The first-stage cyclic A/D converter performs preliminary conversion of the upper bits before the second stage processes the lower bits. This preliminary action allows the residue signal to be generated and prepared in advance, enabling the second stage to operate on pre-processed data and allowing for overlapping operation between stages, thereby improving overall productivity
3Measurement precision
If a complex circuit structure is used to achieve high A/D conversion accuracy, then the measurement precision is improved, but the use of energy increases
Solution Approach 1:
The power consumption is segmented and distributed across two independent conversion stages. The first-stage cyclic A/D converter handles the majority of the conversion complexity for upper bits, while the second-stage A/D converter processes the residue signal with lower complexity requirements. This segmentation allows for optimized power management in each stage, reducing the total power consumption compared to a single high-precision converter that would require uniformly high complexity throughout
Solution Approach 2:
Different conversion accuracy requirements are applied locally to different stages. The first-stage cyclic A/D converter is designed with high precision requirements for upper-bit conversion, while the second-stage A/D converter can operate with relaxed precision requirements for lower-bit conversion. This local quality differentiation allows each stage to be optimized for its specific precision needs, minimizing overall power consumption while achieving the required total conversion accuracy
Data Source
AI summary
An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.