Two-Stage Voltage Signaling for Memory Driver Coordination
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Solution Overview
Problem
Integrated circuit memory devices face challenges in efficiently coordinating voltage drivers to minimize power consumption and prevent non-selected memory cells from becoming conductive during write operations, especially when dealing with memory cells having threshold voltages higher than the initial voltage stage.
Innovation Solution
A two-stage signaling technique is implemented, where the first stage ramps up voltages to place selected memory cells in a conductive state, and a second stage further increases voltages for cells with higher threshold voltages, while using offset voltages and signal routing between circuit patches to prevent non-selected cells from exceeding voltage limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single-stage voltage ramping approach is used, then the device complexity is reduced, but memory cells with higher threshold voltages cannot be properly programmed
Solution Approach 1:
The voltage ramping operation is divided into two distinct stages: a first stage that ramps voltages to an intermediate level, and a second stage that further increases voltages for cells requiring higher threshold voltages. This segmentation allows the system to accommodate memory cells with different threshold voltage requirements while maintaining manageable driver coordination through staged control signals.
2Adaptability or versatility
If higher voltages are applied to program memory cells with higher threshold voltages, then programming capability is improved, but non-selected memory cells may become conductive causing errors
Solution Approach 1:
Offset voltages are applied to non-selected wordlines and bitlines before and during the voltage ramping operation. These offset voltages create a preliminary protective action that prevents non-selected memory cells from reaching their threshold voltage and becoming conductive, even when higher voltages are applied to selected cells for programming.
Solution Approach 2:
Different voltage levels and offset voltages are applied locally to different regions of the memory array based on selection status. Selected memory cells receive the full voltage ramping sequence for programming, while non-selected cells receive offset voltages that maintain them in a non-conductive state, ensuring localized appropriate voltage treatment.
3Device complexity
If voltage ramping is performed without offset voltages, then the device operation is simplified, but power consumption increases and programming accuracy decreases
Solution Approach 1:
Offset voltages are introduced as a control parameter to precisely manage the voltage states of non-selected memory cells during programming operations. By adjusting these offset voltages, the system reduces unnecessary current flow through non-selected cells, thereby lowering power consumption while maintaining accurate programming of selected cells.
Data Source
AI summary
An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.