Two-Terminal ESD Clamp Structure to Prevent False Triggering

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Solution Overview

Problem

Current ESD protection solutions for IC devices, such as SCR and stand-alone grounded gate NMOS, are prone to gate oxide breakdown and false triggering during ESD events, leading to potential permanent damage.

Innovation Solution

A two-terminal IC device with a non-planar architecture is introduced, featuring a deep N-well stacked between a P-type substrate and multiple wells, with optimized doping concentrations and dimensions to modulate snapback characteristics, eliminating the need for additional circuitry and preventing false triggers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SCR or stand-alone grounded gate NMOS is used for ESD protection, then ESD protection function is provided, but gate oxide breakdown and false triggering occur during ESD events

Engineering Contradiction:
ImproveESD protection reliabilityVSAvoidgate oxide breakdown and false triggering
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the doping concentration parameters of the semiconductor regions. Specifically, the first doped semiconductor material has a doping concentration of at least 1×10^19 atoms/cm³, while the second doped semiconductor material has a doping concentration of at least 1×10^20 atoms/cm³. These parameter changes prevent gate oxide breakdown and false triggering while maintaining ESD protection functionality.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite semiconductor structure combining multiple doped regions with different doping types and concentrations. The structure includes a first doped semiconductor material (e.g., P-type) and a second doped semiconductor material (e.g., N-type) stacked in sequence, forming a composite material system that achieves both ESD protection and prevention of gate oxide breakdown.

Inventive Principle:
Principle #40Composite materials

2Reliability

If additional circuitry is added to improve ESD protection, then protection capability is enhanced, but device complexity increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidcircuitry complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the need for additional trigger circuitry and external components. The ESD protection function is achieved through the intrinsic properties of the two-terminal semiconductor device itself, removing the complexity of external SCR circuits or grounded gate NMOS configurations while maintaining effective ESD protection.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The two-terminal semiconductor device performs multiple functions: it provides ESD protection, acts as a clamp device, and prevents false triggering all within a single integrated structure. This multi-functionality eliminates the need for separate circuit components and reduces overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The two-terminal IC device effectively enhances ESD protection by preventing premature breakdown and false triggering, ensuring reliable operation during ESD events without additional circuitry, thus safeguarding victim devices.

Implementation Method 1

optimized doping concentrations and dimensions to modulate snapback characteristics

Methodology Applied
Scientific EffectSnapback effect:

Data Source

PatentEP4478414A1Two-terminal integrated circuit device for electrostatic discharge protection
Publication Date: 2024.12.18 INTEL CORP
  • EP4478414A1 patent drawingFigure 1
  • EP4478414A1 patent drawingFigure 2
  • EP4478414A1 patent drawingFigure 3

AI summary

A two-terminal IC device may be used for ESD protection. The IC device may include a deep N-well may be between a P-type substrate and a group of wells that includes a first P-well, a second P-well, and a N-well. There may be another well between the second P-well and the N-well. A P-type semiconductor structure may be formed in the P-well. Two N-type semiconductor structures may be formed in the second P-well and the N-well, respectively. A contact of the P-type semiconductor structure may be electrically coupled to a contact of the N-type semiconductor structure in the second P-well. The two contacts may constitute the first terminal of the IC device. The contact of the N-type semiconductor structure in the N-well may constitute the second terminal of the IC device. The first P-well may have a greater dimension but lower dopant concentration than the second P-well or the N-well.