U-Shaped Capping Layer for SRAM Gate Stack Isolation

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Solution Overview

Problem

The semiconductor industry faces challenges in fabricating Static Random Access Memory (SRAM) due to difficulties in removing photoresist layers between closely spaced gate stack structures, leading to incomplete etching and potential short circuiting and metal bridge issues as feature sizes decrease.

Innovation Solution

A U-shaped capping layer is formed between gate stack structures to protect the underlying isolation feature from etching during the removal of the resist protective oxide layer, preventing voids and recesses in the inter-layer dielectric layer and thus avoiding short circuiting and metal bridge problems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photoresist layers are removed between closely spaced gate stack structures, then complete etching is achieved, but short circuiting and metal bridge issues occur due to incomplete etching and potential damage to isolation features

Engineering Contradiction:
Improveetching completenessVSAvoidshort circuit prevention
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A U-shaped capping layer is introduced as an intermediary protective structure between closely spaced gate stack structures. This capping layer acts as a mediator that prevents direct contact between conductive materials during subsequent processing steps, thereby avoiding short circuits and metal bridge issues while allowing complete etching to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The U-shaped capping layer is formed in advance before the removal of photoresist layers and subsequent etching processes. This preliminary protective structure is prepared beforehand to prevent potential short circuiting and metal bridge formation that could occur during later manufacturing steps, ensuring isolation feature integrity is maintained throughout the process.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If feature sizes are reduced to increase integration density, then more components are integrated into a given area, but photoresist layer removal becomes more difficult and incomplete etching occurs

Engineering Contradiction:
Improveintegration densityVSAvoidphotoresist removal completeness
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The U-shaped capping layer serves as a protective intermediary that compensates for the difficulties in removing photoresist layers from closely spaced, miniaturized structures. By providing this protective barrier, the process allows for continued reduction in feature size and improvement in integration density without sacrificing etching completeness or creating manufacturing defects.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If U-shaped capping layer is formed between gate stack structures, then isolation feature protection is achieved, but device structure complexity increases

Engineering Contradiction:
Improveisolation feature protectionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The U-shaped capping layer is applied locally only where needed - specifically between closely spaced gate stack structures where short circuiting and metal bridge issues are most likely to occur. This localized approach provides targeted protection to critical isolation features without unnecessarily complicating the entire device structure, maintaining simplicity in regions where protection is not required.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9673200B2Semiconductor device structure and method of manufacturing the same
Publication Date: 2017.06.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9673200B2 patent drawing
  • US9673200B2 patent drawing
  • US9673200B2 patent drawing

AI summary

A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.