U-Shaped Silicon Pillar Memory Device for Low Voltage Erasure
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing capacity and reducing costs, particularly in the manufacturing process of multilayer memories, where forming through holes and stacking insulating and electrode films efficiently is crucial for memory cell formation and select transistor functionality.
Innovation Solution
The semiconductor memory device employs a multilayer body with alternately stacked insulating and electrode films, forming through holes, and depositing memory and semiconductor films, with a step difference in the through holes to enhance impurity implantation efficiency and reduce power consumption by forming a U-shaped silicon pillar and select gate electrode structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional through hole formation and film stacking is used in multilayer memory manufacturing, then device capacity can be increased, but power consumption increases and data erasure efficiency decreases
Solution Approach 1:
The patent applies local quality by forming a step difference at specific locations within the through hole structure. The step difference creates regions with different impurity concentrations - high impurity concentration in the channel formation region and low impurity concentration in the select transistor region. This localized differentiation allows efficient data erasure in the channel region while reducing power consumption in the select transistor region, resolving the contradiction between device capacity and power consumption.
2Ease of manufacture
If conventional through hole formation is used, then manufacturing process is simple, but data erasure efficiency is poor and requires high voltages
Solution Approach 1:
The step difference structure creates localized high impurity concentration regions that enhance hot carrier generation efficiency during erasure operations. This local quality enhancement improves data erasure efficiency and allows operation at lower voltages while maintaining the relatively simple manufacturing process of conventional through hole formation.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming a step difference that creates high impurity concentration in the channel formation region. This parameter change enhances the efficiency of data erasure operations and reduces the voltage required for effective erasure, improving reliability without complicating the manufacturing process.
3Ease of manufacture
If uniform impurity concentration is used throughout the through hole, then manufacturing is easier, but ion implantation efficiency decreases and GIDL operation becomes unstable
Solution Approach 1:
The step difference structure enables local quality control of impurity concentration. The high impurity concentration region is precisely formed in the channel formation region where it is needed for efficient ion implantation and stable GIDL operation, while the select transistor region maintains low impurity concentration. This resolves the contradiction between manufacturing simplicity and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a semiconductor memory device with improved data erasure efficiency at lower voltages, reduced power consumption, and stable GIDL (gate-induced drain leakage) operation, while maintaining high impurity concentration and efficient ion implantation.
Implementation Method 1
a semiconductor film is provided on an inner surface of the first to third through holes
Implementation Method 2
improved data erasure efficiency at lower voltages, reduced power consumption, and stable GIDL (gate-induced drain leakage) operation, while maintaining high impurity concentration and efficient ion implantation
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a multilayer body, a second electrode film provided on the multilayer body, a second insulating film provided on the second electrode film, a semiconductor film, a memory film and a gate insulating film. At boundary between the inner surface of the second through hole and the inner surface of the third through hole, or on the inner surface of the second through hole, a step difference is formed so that an upper side from the step difference is thicker than a lower side from the step difference.