Wafer Level CSP Decoupling via Local UBM Capacitors
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Solution Overview
Problem
Semiconductor devices face challenges in balancing faster operating speeds with reduced power consumption, leading to increased noise due to capacitance and inductance coupling, which causes cross-talk, logic faults, and electromagnetic interference, particularly in the mid-frequency range, where existing PCB-based decoupling solutions are ineffective.
Innovation Solution
The implementation of a semiconductor device with under bump metal (UBM) contacts and capacitors strategically placed between bond pads and distribution lines on the microchip, which includes solder bumps to connect with a printed circuit board, effectively decoupling capacitance and inductance and reducing noise in the mid-frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If faster operating speeds are implemented, then device performance is improved, but noise and electromagnetic interference increase
Solution Approach 1:
A capacitor is introduced as an intermediary component between the power distribution network and ground. The capacitor acts as a mediator that absorbs and shunts high-frequency noise to ground, preventing it from propagating through the power distribution network and causing electromagnetic interference, thus allowing faster operating speeds with reduced noise
Solution Approach 2:
The harmful noise is extracted and isolated from the main power distribution network by providing a dedicated path to ground through the capacitor. This separates the noise from the functional power supply, allowing the device to operate at higher speeds while the noise is contained and directed to ground
2Volume of moving object
If layer reductions are made in the package, then device size is reduced, but routing congestion and cross-talk increase
Solution Approach 1:
The capacitor is placed in a different spatial dimension (on the same layer as bond pads and distribution lines) rather than requiring additional routing layers. This dimensional approach allows decoupling functionality without increasing package vertical height, avoiding routing congestion while reducing cross-talk through proper placement near noise sources
3Reliability
If PCB-based decoupling solutions are used, then power distribution is improved, but effectiveness in mid-frequency range is lost
Solution Approach 1:
Instead of relying on distant PCB-based decoupling, a capacitor is placed locally at the microchip level where the noise is generated. This local placement ensures effectiveness in the mid-frequency range by minimizing the inductance of the decoupling path and providing immediate noise suppression at the source, where PCB solutions are ineffective
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides effective decoupling in the mid-frequency range, reducing noise and improving signal integrity, while being cost-effective and suitable for all wafer level CSP designs, without the mechanical limitations of other solutions.
Implementation Method 1
capacitor contacts the first distribution line and has solder located thereon. A second capacitor contact is located between the first and second solder bumps. It is located over and contacts the second distribution line
Implementation Method 2
routing congestion in the package. Routing congestion can cause cross-talk issues due to capacitance and inductance coupling
Data Source
AI summary
One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.