Asymmetrical Data Rates for UCIe Interconnects
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Solution Overview
Problem
Modern on-chip and off-chip protocols, including the UCIe Specification, do not support asymmetrical data rates within a UCIe interconnect, which limits the ability to optimize data transfer rates according to the specific bandwidth requirements of semiconductor dies, such as SoC and memory chips, where read operations may require higher bandwidth than write operations.
Innovation Solution
The implementation of an asymmetrical data rate capability within the UCIe interconnect using the sideband protocol to establish different data rates for transmit and receive channels, leveraging the forwarded clock feature to support these asymmetrical rates, allowing semiconductor dies to operate at their maximum possible data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If symmetrical data rates are used in UCIe interconnect, then protocol compatibility and simplicity are maintained, but data transfer optimization for specific bandwidth requirements cannot be achieved
Solution Approach 1:
The patent implements asymmetrical data rates in the UCIe interconnect by allowing the transmit channel and receive channel to operate at different data rates. The first data rate for the transmit channel and the second data rate for the receive channel can be independently configured, enabling optimization for specific bandwidth requirements while maintaining protocol compatibility through the sideband protocol mechanism.
2Productivity
If higher data rates are implemented for read operations, then bandwidth requirements for memory access are met, but write operations with lower bandwidth requirements cannot be efficiently handled
Solution Approach 1:
The patent applies different data rates to different directional channels based on their specific bandwidth requirements. The transmit channel can operate at a first data rate optimized for read operations, while the receive channel operates at a second data rate optimized for write operations. This allows each channel to be locally optimized for its primary function, improving read throughput while avoiding unnecessary energy consumption in write operations.
3Productivity
If asymmetrical data rates are implemented, then data transfer optimization is achieved, but protocol complexity increases
Solution Approach 1:
The patent uses the sideband protocol as an intermediary mechanism to manage and coordinate asymmetrical data rates. The sideband protocol handles the complexity of negotiating and maintaining different data rates for transmit and receive channels, allowing the main data path to focus on high-speed transfer while the sideband protocol manages the configuration and synchronization details.
4Productivity
If data rates are optimized for maximum bandwidth, then interconnect throughput increases, but compatibility with existing symmetrical protocols decreases
Solution Approach 1:
The patent implements a universal data rate configuration mechanism that can operate in both symmetrical and asymmetrical modes. The interconnect can negotiate and maintain different data rates for transmit and receive channels independently, while still being compatible with existing symmetrical protocols when both channels require the same data rate. This multi-functional capability allows the system to adapt to various protocol requirements while maximizing data transfer efficiency.
Data Source
AI summary
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.