Ultra-Low-Voltage SRAM Cell with Segmented Write Control
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Solution Overview
Problem
Ultra-low-voltage SRAM designs with bit interleaving structures face write half-select-disturbance, leading to unstable operations and challenges in achieving fast write operations.
Innovation Solution
A 10T SRAM cell design with a cross-coupled inverter pair, N-type and P-type write transistors, and shared NMOS and PMOS headers/footers, along with a differential data-aware write path and dual power supply, to eliminate half-select-disturbance and enhance write capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit interleaving structure is used to mitigate soft errors, then reliability is improved, but write half-select-disturbance occurs leading to unstable operation
Solution Approach 1:
The write word line control is segmented into four independent signals (WWLP0, WWLP1, WWLN0, WWLN1) that can be independently activated. This segmentation allows precise control of write operations to eliminate half-select disturbance while maintaining bit interleaving structure for soft error mitigation.
Solution Approach 2:
Different write word line signals are applied to different bit pairs within the same row. The local quality of write control is optimized by enabling write operations only in specific column regions where needed, preventing disturbance to other columns while maintaining reliability through selective write activation.
2Use of energy by moving object
If supply voltage is reduced to achieve ultra-low energy consumption, then energy efficiency is improved, but probability of soft error increases
Solution Approach 1:
The bit interleaving structure segments storage into pairs of bits with independent control. This segmentation allows the system to operate at ultra-low voltages while maintaining reliability through redundant storage paths and selective write control that prevents half-select disturbance.
Solution Approach 2:
The invention changes the control parameters by introducing dual-polarity write word lines (positive and negative phases) and independent column selection signals. These parameter changes enable reliable operation at ultra-low voltages by providing multiple control dimensions for error mitigation.
3Stability of the object's composition
If write word line structure with rows and columns crossed is used to eliminate half-select-disturbance, then write stability is improved, but write capability is significantly degraded
Solution Approach 1:
The write capability is dynamically optimized by enabling write operations only when both row and column select signals are active. The differential write word line signals (WWLP and WWLN) provide dynamic control that maintains high write capability while ensuring stability through conditional write activation.
Solution Approach 2:
Write capability is locally optimized by applying write voltage only to selected column regions through independent column select signals. This local quality approach maintains high write speed in active regions while preventing disturbance in inactive regions, resolving the contradiction between stability and capability.
Data Source
AI summary
An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.