Ultra-Thin Multi-Die Face-to-Face WLCSP Interconnect Design
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to create robust interconnect structures between stacked semiconductor die, particularly for thin die, to prevent die chipping and cracking while achieving a smaller footprint and higher performance.
Innovation Solution
The development of an ultra-thin multi-die face-to-face WLCSP (Wafer Level Chip Scale Package) using conductive pillars and micro-bumps for vertical electrical interconnection, along with a double-molded structure for enhanced thermal and electrical performance, and additional carriers for structural support to minimize chipping and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used for thin semiconductor die, then the manufacturing process is simpler, but the die are susceptible to chipping and cracking
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: micro-bumps for fine-pitch electrical connection, conductive pillars for vertical through-silicon interconnection, and mold compounds for mechanical support. This segmentation allows each component to specialize in protecting against specific failure modes while maintaining overall structural integrity.
Solution Approach 2:
The patent employs composite material structures including Cu-plated conductive pillars embedded in mold compound, multi-layer interconnect stacks with alternating conductive and insulating layers, and hybrid bump structures combining solder and encapsulant materials. These composites provide both mechanical reinforcement and electrical functionality simultaneously.
2Length of stationary object
If the package thickness is reduced to achieve ultra-thin profile, then the footprint is smaller, but the structural support is insufficient
Solution Approach 1:
The patent transitions from planar support structures to three-dimensional vertical interconnects through conductive pillars extending through the silicon substrate. This dimensional change enables mechanical reinforcement without increasing lateral footprint, achieving ultra-thin profile while maintaining structural integrity through vertical load distribution.
Solution Approach 2:
Mold compounds are applied beforehand to embed and protect the conductive pillars and micro-bumps, creating a cushioning matrix that distributes mechanical stresses before they can concentrate on critical interconnect elements. This preventive encapsulation reduces susceptibility to chipping and cracking during handling and operation.
3Reliability
If conductive pillars and micro-bumps are used for vertical interconnection, then the electrical connection is more robust, but the manufacturing process becomes more complex
Solution Approach 1:
Conductive pillars are formed through the silicon substrate before die stacking, and micro-bumps are pre-formed on the die surfaces before assembly. This preliminary preparation of interconnect structures enables automated pick-and-place assembly processes, reducing manufacturing complexity despite the advanced interconnect architecture.
Solution Approach 2:
Mold compounds serve as intermediary materials that simultaneously provide mechanical support, electrical insulation, and stress distribution for the conductive pillars and micro-bumps. This intermediary layer simplifies manufacturing by enabling single-step encapsulation processes that protect multiple interconnect elements without requiring separate handling for each component.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a robust, ultra-thin package with improved thermal and electrical performance, reducing the risk of die chipping and cracking, and enabling smaller, more efficient semiconductor devices with enhanced functionality.
Implementation Method 1
The vertical electrical interconnection can be accomplished with conductive through silicon vias (TSV), through hole vias (THV), or Cu-plated conductive pillars
Implementation Method 2
a double-molded structure for enhanced thermal and electrical performance
Data Source
AI summary
A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.