Ultra-thin Embedded Semiconductor Package with Planar Interconnects
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Solution Overview
Problem
Existing power semiconductor device packaging structures face challenges with high inductance, size, and cost due to the use of wirebonds and multi-layer substrates, which affect efficiency and reliability, and require additional processing steps.
Innovation Solution
A semiconductor package structure with power overlay (POL) interconnects that forms all electrical and thermal interconnections using a dielectric layer, embedding material, and metal interconnects, eliminating the need for wirebonds and multi-layer substrates, allowing for an ultra-thin, miniaturized design with I/O connections for external circuit connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonds and multi-layer substrates are used for electrical interconnections, then reliable electrical connections are achieved, but parasitic inductance increases and efficiency decreases
Solution Approach 1:
The patent extracts and eliminates wirebonds and multi-layer substrates from the packaging structure, replacing them with a planar interconnect architecture where metal traces are formed directly on a single substrate layer, removing the sources of parasitic inductance while maintaining electrical connectivity
Solution Approach 2:
The invention transitions from a three-dimensional vertical stacking architecture (wirebonds connecting multiple substrate layers) to a two-dimensional planar interconnect layout, spreading electrical connections across the substrate plane to reduce current loop area and associated inductance
2Reliability
If wirebonds and leads are used for electrical connections, then electrical connectivity is provided, but package height increases
Solution Approach 1:
The patent removes wirebonds and leadframe structures that contribute to package height, replacing them with a low-profile planar interconnect system where electrical connections are made through copper traces and vias within a single substrate layer, dramatically reducing vertical dimension
Solution Approach 2:
The invention redistributes electrical connections from a vertical arrangement (wirebonds extending upward from chip to package pins) to a horizontal planar arrangement (traces routed across the substrate), converting vertical space consumption into lateral routing that maintains a thin package profile
3Reliability
If DBC substrate and wirebonds are used for thermal and electrical connections, then thermal connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the functions of DBC substrate, wirebonds, and additional interconnect layers into a single integrated planar interconnect structure where copper traces and vias on a ceramic or polymer substrate simultaneously provide both thermal conduction pathways and electrical connections, eliminating the need for separate thermal management components
Solution Approach 2:
The planar interconnect substrate serves multiple functions simultaneously: it provides mechanical support for the semiconductor device, conducts heat away from the device through thermally conductive pathways, establishes electrical connections through patterned copper traces, and provides a mounting surface for additional components, replacing multiple specialized components with a single multi-functional structure
Data Source
AI summary
A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.