UMOSFET Split Gate and Protection Layer Design
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Solution Overview
Problem
Existing UMOSFET structures face issues with damage from critical electric fields, high on-resistance, and slow switching between conducting and blocking states due to design defects and high gate-drain capacitance.
Innovation Solution
A UMOSFET structure with a semiconductor protection layer and split gate design, featuring a trench with an insulating layer and a semiconductor protection layer below the trench to prevent electric field damage, and a current spread layer to reduce resistance, along with a split gate separated from the main gate by an insulating layer to minimize capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional UMOSFET structure with a single gate is used, then the structure is simple, but the critical electric field damages the insulating layer at the corner in the off-state
Solution Approach 1:
The gate structure is segmented into a main gate and a split gate, separated by an insulating layer. This segmentation redistributes the electric field distribution, preventing the critical electric field from concentrating at the corner and damaging the insulating layer, thus resolving the contradiction between reliability and structural simplicity.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the main gate and the split gate. This intermediary element modifies the electric field distribution pattern, acting as a buffer that prevents direct electric field concentration at the corner, thereby protecting the insulating layer while maintaining a relatively simple overall structure.
2Speed
If the gate extends deeply into the N-CSL to increase control, then the gate-drain capacitance increases, but the switching time becomes longer
Solution Approach 1:
The gate is segmented into main gate and split gate portions, with the split gate extending deeper into the N-CSL. This segmentation allows the main gate to maintain lower capacitance for faster switching, while the split gate provides enhanced control over the channel, thus resolving the contradiction between switching speed and control effectiveness.
Solution Approach 2:
Different portions of the gate structure have different extension depths into the N-CSL. The split gate extends deeper locally to provide enhanced control where needed, while the main gate maintains a shallower extension to minimize overall capacitance, achieving both fast switching and effective control through localized structural optimization.
3Reliability
If no current spread layer is used, then the structure is simpler, but the on-resistance is higher
Solution Approach 1:
The N-current spread layer serves multiple functions: it reduces on-resistance by spreading current distribution, provides an additional interface for the split gate to extend into for enhanced control, and contributes to the overall electric field management. This multi-functional element reduces on-resistance without significantly increasing structural complexity.
4Reliability
If a semiconductor protection layer is added below the trench, then the insulating layer is protected from electric field damage, but the device structure becomes more complex
Solution Approach 1:
The semiconductor protection layer is merged with the existing N-drift region structure, forming an integrated protective configuration. This merging approach provides insulating layer protection through the electric field redistribution achieved by the combined structure, while minimizing the increase in overall device complexity by utilizing existing structural elements.
Data Source
AI summary
A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.