Under Ball Release Layer for Solder Pad Bonding

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Solution Overview

Problem

The challenge in chip packaging lies in redistributing increasing chip contacts on a downsized chip surface, leading to electrical reliability issues due to small gaps between contacts, and existing methods result in encapsulant overflow and contamination, with the redistribution layer having limited bonding strength after carrier removal.

Innovation Solution

A package structure and manufacturing method where a redistribution layer is formed on a carrier, with a patterned circuit layer and under ball release layers, allowing the chip to be encapsulated and solder balls to be formed with increased bonding area and strength by forming under ball release layers that cover pads, enhancing electrical connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the redistribution layer is formed on the active surface of the chip, then the chip area is increased, but the encapsulant may overflow and contaminate the active surface of the chip

Engineering Contradiction:
Improvechip areaVSAvoidencapsulant contamination
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The redistribution layer is formed on the carrier substrate before the chip is mounted and encapsulated. This preliminary positioning allows the encapsulant to be applied without risk of overflowing onto the chip's active surface, as the redistribution layer extends beyond the chip boundaries on the carrier. The chip is then mounted on this pre-formed redistribution layer, and encapsulation proceeds without contamination risk.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If the redistribution layer is formed on the carrier and the carrier is removed, then the chip area is increased, but the exposed redistribution layer is planar and has less bonding strength

Engineering Contradiction:
Improvechip areaVSAvoidbonding strength
Core Design Contradiction:
Area of stationary objectVSStrength

Solution Approach 1:

The under ball release layer is applied selectively to the pad regions of the redistribution layer, creating local quality enhancement at the bonding interfaces. This layer provides increased surface area and improved bonding characteristics specifically where solder balls need to attach, while leaving other areas of the redistribution layer in their original state. The result is enhanced bonding strength at critical locations without requiring changes to the entire redistribution layer structure.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If the number of chip contacts increases, then the chip functionality is improved, but the gap between contacts becomes too small affecting electrical reliability

Engineering Contradiction:
Improvenumber of chip contactsVSAvoidelectrical reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The redistribution layer extends the contact array into additional spatial dimensions beyond the chip surface. By distributing contacts across the larger area of the redistribution layer on the carrier substrate, the density of contacts is reduced while maintaining the total number of contacts. This dimensional expansion allows adequate spacing between contacts for reliable soldering while preserving all required electrical connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10522438B2Package structure having under ball release layer and manufacturing method thereof
Publication Date: 2019.12.31 IND TECH RES INST
  • US10522438B2 patent drawing
  • US10522438B2 patent drawing
  • US10522438B2 patent drawing

AI summary

A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.