Semiconductor Under-Bump Layer Corrosion Protection
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Solution Overview
Problem
In semiconductor devices using Wafer Level-Chip Size Package (WL-CSP) technology, the under-bump layer is prone to corrosion and stripping from the stress relaxation layer due to moisture exposure, leading to unreliable electrical connections.
Innovation Solution
A semiconductor device configuration that includes a stress relaxation layer with a protective layer covering the entire periphery of the under-bump layer, preventing corrosion and stripping, and featuring a barrier layer made of titanium or nickel with a connection pad having solder wettability, further protected by a solder terminal that covers the side face of the connection pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the under-bump layer is formed to cover the electrode pad and through-hole, then electrical connection is achieved, but the exposed side faces of the barrier layer and metal plating layer are vulnerable to moisture corrosion and stripping
Solution Approach 1:
A protective layer is formed to cover the side faces of the under-bump layer, barrier layer, and metal plating layer. This protective film acts as a barrier shell that prevents moisture from reaching and corroding the exposed metallic surfaces, thereby resolving the vulnerability of the under-bump structure while maintaining its electrical connection function
Solution Approach 2:
The protective layer serves as an intermediary barrier between the moisture environment and the under-bump layer components. It mediates the interaction by blocking moisture contact with the barrier layer and metal plating layer, preventing corrosion and stripping while allowing the electrical connection to function normally
2Ease of operation
If the barrier layer and metal plating layer are exposed to achieve electrical connection, then solder ball attachment is enabled, but corrosion of these layers causes stripping from the stress relaxation layer
Solution Approach 1:
The protective layer forms a protective shell over the side faces of the barrier layer and metal plating layer, preventing moisture-induced corrosion that would otherwise weaken the adhesion between these layers and the stress relaxation layer, thereby maintaining attachment strength while allowing solder ball attachment to proceed
3Ease of manufacture
If the side faces of the under-bump layer are left exposed for electrical connection, then solder terminal formation is simplified, but the under-bump layer becomes susceptible to corrosion and stripping
Solution Approach 1:
The protective layer is formed to cover the side faces of the under-bump layer, creating a protective environment that prevents corrosion while allowing the solder terminal to be formed on top. This resolves the contradiction by protecting the vulnerable side faces without interfering with the solder terminal formation process on the upper surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the connection reliability by preventing corrosion and stripping of the under-bump layer from the stress relaxation layer, ensuring stable electrical connections and improved durability against moisture exposure.
Implementation Method 1
the barrier layer 88 (for example, titanium, tungsten titanium, and the like) and a metal plating layer 89 (for example, copper, gold, and the like) formed on the barrier layer 88
Implementation Method 2
The solder ball 84 is provided on the surface of the metal plating layer 89 and electrically connected with the electrode pad 85 via the metal plating layer 89 and the barrier layer 88
Implementation Method 3
a stress relaxation layer 83 (polyimide, for example) laminated on the surface protective film 81
Data Source
AI summary
A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; an under-bump layer formed so as to cover a face exposed in the opening on the internal pad, an inner face of the opening and a circumference of the opening on the stress relaxation layer; a solder terminal for electrical connection with outside formed on the under-bump layer; and a protective layer formed on the stress relaxation layer, encompassing a periphery of the under-bump layer and covering a side face of the under-bump layer.