Underground Bit Line DRAM Cell Reduces Capacitance
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Solution Overview
Problem
Conventional DRAM structures face challenges in reducing bit line capacitance, which affects the number of DRAM cells that can be connected to a bit line and the voltage requirements for successful sensing and amplification.
Innovation Solution
The semiconductor memory structure incorporates an underground bit line design with a recess gate access transistor and a storage capacitor, reducing the bit line capacitance per cell to one-fourth of the conventional value by optimizing the cell topography and using TCAD simulations to minimize capacitance between the bit line and other components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM cell design is used with bit line connected to access transistor drain, then DRAM cells can be connected to bit line, but bit line capacitance per cell is high (40×10^-3 fF)
Solution Approach 1:
The patent introduces a local word line that connects to the gate conductive region of the access transistor, creating a new dimensional connection path. This allows the bit line to be disconnected from the access transistor drain while maintaining cell connectivity through the local word line gate path, thereby reducing bit line capacitance from 40×10^-3 fF to 10×10^-3 fF per cell.
Solution Approach 2:
The patent extracts the bit line connection from the access transistor drain terminal and relocates it to connect directly to the sense amplifier. This separation removes the capacitive coupling between the bit line and access transistor, eliminating a major source of bit line capacitance while preserving read/write functionality through the local word line.
2Speed
If bit line capacitance is reduced, then RC time constant is reduced and operation speed is improved, but voltage requirements for sensing and amplification change
Solution Approach 1:
The patent changes the electrical parameters of the bit line by reducing its capacitance from 40×10^-3 fF to 10×10^-3 fF per cell. This parameter change directly reduces the RC time constant, enabling faster operation speeds. The local word line gate connection provides enhanced voltage control to maintain proper sensing and amplification levels despite the reduced capacitance.
3Use of energy by moving object
If local word line is introduced to connect to gate conductive region, then bit line capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent segments the word line function into two parts: a global word line that provides overall control and a local word line that specifically connects to the gate conductive region of the access transistor. This segmentation allows the local word line to serve the dual purpose of reducing bit line capacitance while maintaining simple integration with existing DRAM cell structures.
Data Source
AI summary
A semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.