Undermount Passive Devices in Semiconductor Chip Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor chip packages face inefficiencies in power supply noise reduction due to long electrical pathways and high equivalent series inductance in decoupling capacitors, which diminish their filtering effectiveness.
Innovation Solution
The solution involves mounting passive devices, such as capacitors, on the underside of the carrier substrate with a gap between the substrate and the printed circuit board, allowing for direct and shorter electrical connections to the board, thereby reducing pathway length and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are mounted to the die side or underside of the carrier substrate using conventional methods, then power supply noise filtering is provided, but the electrical pathway length becomes too long which diminishes the effectiveness of the decoupling capacitor
Solution Approach 1:
The patent positions decoupling capacitors in the vertical dimension by mounting them on the underside of the carrier substrate and extending their terminals through the substrate thickness. This three-dimensional arrangement creates direct vertical electrical pathways from the die to the capacitors and to external circuitry, dramatically reducing pathway length compared to conventional planar mounting on the die side.
Solution Approach 2:
The decoupling capacitors are nested within the carrier substrate structure itself, with capacitor bodies positioned in cavities or recesses of the substrate and terminals extending through the substrate. This nesting integrates the capacitors into the substrate's three-dimensional architecture, minimizing the electrical distance between power delivery network elements and the decoupling capacitors.
2Area of stationary object
If decoupling capacitors are mounted to the underside of the carrier substrate, then space is saved on the die side, but the capacitors are not tied directly to the printed circuit board resulting in high equivalent series inductance
Solution Approach 1:
The capacitor structures are nested within the carrier substrate with terminals extending through the substrate thickness. This integration creates direct electrical pathways from the capacitors to both the die (via through-substrate connections) and to external circuitry on the printed circuit board, eliminating the need for long return paths through the substrate metallization and reducing equivalent series inductance.
Solution Approach 2:
The carrier substrate is designed with localized through-substrate vias or conductive pathways positioned directly beneath the decoupling capacitors on the underside. This creates low-inductance connection points that directly tie the capacitors to external circuitry, while the rest of the substrate maintains its standard layered structure for signal and power distribution.
Data Source
AI summary
Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.