Unified AL Setting Circuit for 3D Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices lack an efficient mechanism to adjust additive latency (AL) settings, particularly in 3D structures, leading to operational delays due to increased TSV load, requiring separate circuit configurations for common and 3D structures, which is inefficient.
Innovation Solution
An integrated circuit with an AL setting circuit that includes a decoding unit and a decoding operation control unit, utilizing a stack information signal to generate AL setting signals and activate reserved or complementary setting signals, allowing AL to be set in a different range depending on the device structure, enabling a single circuit to function in both common and 3D semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional AL setting circuit is used in 3D semiconductor memory devices, then the circuit structure is simple, but operational delays occur due to increased TSV load
Solution Approach 1:
The AL setting circuit dynamically adjusts the additive latency value based on the stack information signal. When a stack structure is detected, the circuit automatically selects a larger AL value to compensate for TSV-induced delays, whereas conventional circuits use fixed AL values regardless of structure type
Solution Approach 2:
The circuit changes the AL parameter based on the device structure. The decoding unit generates different AL setting signals (ALCL_0 to ALCL_3) corresponding to different stack configurations, allowing the system to optimize timing parameters for either common or 3D structures
2Loss of time
If separate circuit configurations are used for common and 3D semiconductor memory devices, then operational delays are compensated, but device complexity increases
Solution Approach 1:
A single AL setting circuit is designed to serve both common and 3D semiconductor memory devices. The circuit includes a stack information signal input that automatically configures the appropriate AL values based on the device type, eliminating the need for separate circuit designs
Solution Approach 2:
The stack information signal acts as an intermediary that informs the AL setting circuit about the device structure type. This signal enables the circuit to automatically select the appropriate AL configuration without requiring separate hardwired circuits for different device types
3Reliability
If AL values are increased to compensate for TSV load in 3D structures, then operational timing is improved, but read latency increases
Solution Approach 1:
The circuit applies different AL values to different operational contexts based on the device structure. For 3D structures, larger AL values are used specifically to compensate for TSV delays, while common structures use smaller AL values to maintain faster read latency. This localized optimization ensures timing accuracy is improved only where needed
Data Source
AI summary
An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.