Unified Memory BIST Controller for Multi-Type SoC Testing
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Solution Overview
Problem
Existing system-on-chip (SOC) devices face inefficiencies and increased complexity due to the need for separate BIST controllers for various memory types, leading to excessive area overhead and complexity in testing and diagnosis.
Innovation Solution
A unified memory BIST system with a single controller that generates test instructions for multiple memory types, including single port and non-single port memories, using a programmable operation code structure to perform thorough testing, repair, and diagnosis, reducing the need for memory-type specific controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate BIST controllers are used for each memory type, then testing coverage for different memory types is improved, but area overhead and device complexity increase
Solution Approach 1:
The patent implements a universal BIST controller that can test multiple memory types (single-port SRAM, multi-port SRAM, TCAM) through a single controller instance. The controller uses operation codes to configure itself for different memory types, eliminating the need for separate dedicated controllers for each memory type while maintaining comprehensive testing coverage.
Solution Approach 2:
The BIST controller is designed with dynamic reconfigurability, allowing it to change its testing behavior based on the target memory type. The controller can be programmed with different operation codes to adapt its testing sequences, patterns, and protocols to match the specific requirements of different memory types, making it a flexible and dynamic testing solution.
2Reliability
If separate BIST controllers are used for each memory type, then memory-type specific testing is improved, but area overhead increases
Solution Approach 1:
The patent implements a universal BIST controller that can test multiple memory types (single-port SRAM, multi-port SRAM, TCAM) through a single controller instance. The controller uses operation codes to configure itself for different memory types, eliminating the need for separate dedicated controllers for each memory type while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent merges the functionality of multiple separate BIST controllers into a single unified controller. By combining the testing capabilities for different memory types into one controller, the total area overhead is reduced while still providing specialized testing for each memory type through software configuration rather than hardware duplication.
3Adaptability or versatility
If multiple BIST controllers are used, then testing flexibility for different memory types is improved, but system complexity increases
Solution Approach 1:
The BIST controller is designed with dynamic reconfigurability, allowing it to change its testing behavior based on the target memory type. The controller can be programmed with different operation codes to adapt its testing sequences, patterns, and protocols to match the specific requirements of different memory types, making it a flexible and dynamic testing solution.
Solution Approach 2:
The patent uses operation codes as configurable parameters that change the behavior of the BIST controller. By modifying the operation code parameters, the same hardware controller can adapt to different memory types and testing requirements, providing flexibility without increasing hardware complexity.
Data Source
AI summary
A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.