Unified Processing Unit for Mixed-Size Instruction Execution

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Solution Overview

Problem

Current System-on-a-Chip (SoC) designs require significant silicon area and increased electrical power consumption due to the implementation of a co-processor for handling different instruction sizes, and existing solutions either require additional chips or complex co-processor setups.

Innovation Solution

The processing unit is designed to determine its operational conditions based on the size of the application program instructions and configure itself to execute instructions of varying sizes, eliminating the need for a co-processor by generating a reboot command to reconfigure and reboot for executing application program instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a co-processor is implemented to handle different instruction sizes, then the processing capability is improved, but the silicon area and electrical power consumption increase significantly

Engineering Contradiction:

Improveprocessing capabilityVSAvoidsilicon area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges the co-processor functionality into the main processing unit by providing it with multiple instruction buffers (first buffer for 32-bit instructions, second buffer for 64-bit instructions) and a unified instruction decoding mechanism. This allows a single processing unit to handle different instruction sizes without requiring separate co-processor hardware, thereby reducing silicon area while maintaining processing capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The processing unit is designed with universal functionality to execute both 32-bit and 64-bit instructions through a single unified architecture. The instruction buffer is configured to store different instruction sizes, and the decoding logic can interpret both instruction formats, eliminating the need for dedicated co-processor hardware and reducing overall device complexity and area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a co-processor is implemented to handle different instruction sizes, then the processing capability is improved, but the electrical power consumption increases

Engineering Contradiction:

Improveprocessing capabilityVSAvoidelectrical power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

By merging co-processor functions into the main processing unit with unified instruction buffers and decoding logic, the patent eliminates the need for separate co-processor power domains and inter-processor communication interfaces. This consolidation reduces overall power consumption while maintaining the ability to process both 32-bit and 64-bit instructions.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If two systems on different chips are used to handle different instruction sizes, then the adaptability is improved, but the device complexity increases

Engineering Contradiction:

ImproveadaptabilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple instruction size handling capabilities into a single integrated processing unit with unified control logic. Instead of requiring two separate chip systems, the invention provides a single chip solution with configurable instruction buffers and decoding logic that can adapt to different instruction sizes, thereby reducing device complexity while maintaining adaptability.

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If a co-processor is implemented, then the processing capability for different instruction sizes is improved, but the system complexity increases

Engineering Contradiction:

Improveprocessing capabilityVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges co-processor functionality into the main processing unit by providing it with multiple instruction buffers (first buffer for 32-bit instructions, second buffer for 64-bit instructions) and a unified instruction decoding mechanism. This allows a single processing unit to handle different instruction sizes without requiring separate co-processor hardware, thereby reducing silicon area while maintaining processing capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11614949B2Method and device for managing operation of a computing unit capable of operating with instructions of different sizes

Publication Date: 2023.03.28 STMICROELECTRONICS (GRENOBLE 2) SAS

AI summary

An integrated circuit comprises a processing unit configured for booting up with a set of boot instructions, then for determining the size of the instructions of an application programme and potentially rebooting on its own initiative, while being reconfigured, in order for it to execute the instructions of the application program. Only one boot memory is needed as a consequence.