Unified Signal Processor with SIMD Microcoding for MIMO Processing
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Solution Overview
Problem
Existing communication devices face challenges in efficiently performing various signal processing operations, such as channel estimation and MIMO detection, due to the cumbersome nature of employing designated digital signal processors for each technique, which can be improved by adopting a unified processor that supports flexible and adaptive signal processing.
Innovation Solution
Implementing a unified processor with a SIMD architecture and microcoded engine that performs parallel computations on multiple data points, enabling simultaneous processing of signal components like subcarriers using a controller and processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If designated digital signal processors are employed for each signal processing technique, then the processing can be performed with respect to received communication signals, but the device complexity increases and flexibility decreases
Solution Approach 1:
The patent implements a unified processor that can perform multiple signal processing operations including channel estimation, MIMO detection, MIMO decoding, and error correction through a single architecture. The processor uses a microcoded engine with configurable parameters that allow it to adapt to different processing techniques, eliminating the need for separate designated processors for each function.
Solution Approach 2:
The processor employs dynamic reconfiguration capabilities where processing parameters, data flow configurations, and operational modes can be changed during operation. The microcoded engine allows flexible programming to adapt to different signal processing requirements, enabling the system to dynamically switch between different processing techniques without hardware changes.
2Productivity
If multiple designated processors are used for different signal processing operations, then comprehensive processing capability is achieved, but the time constraints for processing cannot be met
Solution Approach 1:
The patent merges multiple signal processing functions into a single unified processor architecture. By combining channel estimation, MIMO detection, decoding, and error correction capabilities in one processor, the system eliminates the time delays associated with data transfer between multiple separate processors and achieves better overall processing throughput within time constraints.
Solution Approach 2:
The unified processor enables continuous processing operations without interruption for data transfer between separate processing units. The integrated architecture allows seamless flow of data through different processing stages, maintaining continuous useful action and maximizing processing throughput within available time.
3Productivity
If a unified processor with SIMD architecture is implemented, then parallel computation efficiency increases, but the device complexity increases
Solution Approach 1:
The unified processor employs a SIMD (Single Instruction Multiple Data) architecture that segments processing into multiple parallel execution units. Each processing element can operate independently on different data points simultaneously, achieving parallel computation efficiency while managing complexity through standardized segmented architecture.
Solution Approach 2:
The processor uses parameter-based configuration where the same hardware architecture can be programmed with different parameters to perform various signal processing functions. The microcoded engine allows flexible parameter adjustment to optimize parallel processing efficiency for different operations without requiring separate hardware designs.
Data Source
AI summary
A processor may include an interface configured to receive input data and instructions, and to provide processed data, a shared memory configured to store the received input data, an instruction memory configured to store the received instructions, a plurality of processing elements configured to perform a first set of arithmetic operations. The processor may further include a controller configured to control the plurality of processing elements and one or more accelerators based on the received instructions to obtain the processed data, by which the plurality of processing elements performs the first set of arithmetic operations and the one or more accelerators perform a second set of arithmetic operations based on the received input data stored in the shared memory.