Unit Cell Capacitor Layout for High Capacitance Without Breakdown
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Solution Overview
Problem
There is a demand for multilayer capacitors with higher capacity in a smaller form factor to meet the miniaturization and thinning requirements of electronic devices.
Innovation Solution
The capacitor design includes a substrate with unit capacitor cells featuring lower and upper electrodes connected through internal connection layers, external electrodes, and a dielectric layer, allowing for high-density electrode formation in a compact space, with electrodes connected in series to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If internal electrodes are densely packed in a small space to achieve high capacity, then capacitance increases, but the risk of breakdown phenomena increases
Solution Approach 1:
The capacitor is divided into multiple unit capacitor cells (first, second, third, and fourth unit capacitor cells) arranged in a 2x2 matrix. Each unit cell contains separated lower and upper electrodes with insulating films between them, preventing direct contact and breakdown while maintaining high electrode density for high capacitance
Solution Approach 2:
Insulating films are introduced as intermediary layers between adjacent lower electrodes and between adjacent upper electrodes in different unit capacitor cells. These insulating films prevent direct electrical contact between electrodes that would cause breakdown, while still allowing the electrodes to be densely packed for high capacitance
2Reliability
If multiple unit capacitor cells are connected in series to increase breakdown voltage, then reliability improves, but device complexity increases
Solution Approach 1:
Multiple unit capacitor cells are merged into a single integrated capacitor structure where the lower electrodes and upper electrodes of adjacent unit cells are electrically connected through conductive paths. This combining approach achieves series connection for high breakdown voltage while maintaining a compact, unified device structure rather than separate components
Solution Approach 2:
The capacitor utilizes a three-dimensional stacked arrangement with lower electrodes and upper electrodes positioned at different vertical levels (z-dimension) and horizontal positions (x-y plane). This spatial arrangement allows series connection of multiple unit cells without increasing the device footprint, managing complexity through vertical integration rather than horizontal expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high capacitance in a small area by densely packing internal electrodes, reducing equivalent series resistance and inductance, and increasing breakdown voltage while minimizing the risk of breakdown phenomena.
Implementation Method 1
each of the unit capacitor cells includes: a lower electrode; an upper electrode disposed on the lower electrode
Implementation Method 2
a plurality of unit capacitor cells disposed on the substrate
Data Source
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AI summary
An aspect of the present disclosure provides a capacitor including: a substrate; and a plurality of unit capacitor cells disposed on the substrate, wherein each of the unit capacitor cells includes: a lower electrode; and an upper electrode disposed on the lower electrode, the lower electrode included in a first unit capacitor cell among the unit capacitor cells is connected to the upper electrode included in a second unit capacitor cell among the unit capacitor cells.