Universal Logic Memory Cell Using Triple-Gate Silicon Devices
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Solution Overview
Problem
Conventional logic memory technologies face challenges in implementing ternary logic operations, memory functions, and integration limitations due to the separation of processor and memory, high power consumption, and reliance on non-silicon materials, leading to inefficiencies in data processing and integration.
Innovation Solution
A universal logic memory cell utilizing triple-gate silicon devices with a positive feedback loop, capable of performing ternary logic operations and memory functions, integrated into a single structure using a conventional CMOS process, and maintaining logical operation values through channel mode reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic memory technology uses volatile memory devices (SRAM, DRAM), then stable operation is achieved, but a large number of transistors are required which limits overall area and power consumption
Solution Approach 1:
The patent combines computational logic functions and memory storage functions into a single integrated cell structure. The same triple-gate silicon device performs both logic operations (AND, OR, NOT, NAND, NOR, XOR) and stores ternary logic values (0, 1, 2), eliminating the need for separate processor and memory components. This merging reduces the number of transistors required while maintaining stable operation through the device's inherent positive feedback mechanism.
Solution Approach 2:
The triple-gate silicon device is designed as a universal component that can perform multiple functions: it acts as both a logic gate and a memory element. By controlling the gate voltages (CG1, CG2, CG3), the same device structure can implement different logic operations and store ternary values, making it a multi-functional universal cell that replaces traditional specialized components.
2Ease of manufacture
If von Neumann-based systems separate processor and memory, then modular architecture is achieved, but data transmission time and latency increase
Solution Approach 1:
The patent eliminates the physical separation between processor and memory by integrating both functions into the same cell. The triple-gate silicon device simultaneously performs computational operations and stores data, removing the need for data transmission between separate components. This reduces latency and data transmission time while maintaining the benefits of standardized cell design for ease of manufacture.
3Duration of action of stationary object
If nonvolatile memory devices (ReRAM, MRAM, PCRAM) are used for logic memory, then memory retention is improved, but complex non-silicon processes are required which reduce device uniformity and stability
Solution Approach 1:
The patent uses uniform triple-gate silicon devices throughout the system, maintaining material homogeneity (silicon-based) while achieving both volatile and nonvolatile operation modes. The same device structure and fabrication process can produce cells that operate in different modes depending on voltage control, ensuring high device uniformity and stability without requiring complex non-silicon materials or processes.
4Quantity of substance
If multiple-valued logic systems are implemented to overcome binary logic limitations, then information density is improved, but power consumption increases due to leakage current
Solution Approach 1:
The triple-gate silicon device incorporates a positive feedback mechanism where the output of the logic operation is fed back to maintain the stored state. This feedback loop allows the device to retain ternary logic values (0, 1, 2) without continuous power consumption, reducing leakage current effects. The feedback ensures stable state maintenance while enabling multiple-valued logic operation for higher information density.
5Adaptability or versatility
If devices using NDR, NDT, or QDs are used for multiple-valued logic, then logic operation capability is improved, but reliability and operating temperature limitations occur
Solution Approach 1:
The patent achieves multiple-valued logic capability by changing the voltage parameters (gate voltages CG1, CG2, CG3) of conventional triple-gate silicon devices rather than using exotic materials or structures. By controlling the voltage levels applied to the gates, the device can operate in different modes (volatile, nonvolatile, logic operation) and represent multiple logic states, maintaining high reliability and broad operating temperature ranges inherent to silicon devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances processing speed, reduces power consumption, and improves integration by fusing logical operations and storage functions, while maintaining logical operation values without structural changes.
Implementation Method 1
a universal logic memory cell that provides ternary logic operation function and memory function using a triple-gate silicon device driven by a positive feedback loop
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices. The universal logic memory cell according to one embodiment of the present disclosure may perform a ternary logic operation function and a memory function using triple-gate silicon devices driven by a positive feedback loop.