Stacked Nanosheet Transistor Layout for Threshold Voltage Tuning
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Solution Overview
Problem
Existing semiconductor devices face challenges in controlling threshold voltage and managing short channel effects in multi-gate transistors, particularly in structures with stacked nanosheets, where conventional designs do not effectively utilize conductive layers to optimize electrical performance.
Innovation Solution
A semiconductor device design featuring a gate electrode that surrounds lower and upper nanosheets with a conductive layer positioned only on the surfaces of upper nanosheets, excluding the lower nanosheets, allowing for independent control of threshold voltage through the conductive layer's placement and material selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-gate transistor structure is used to improve current control capability, then current control capability is improved, but device complexity increases
Solution Approach 1:
The transistor channel is segmented into multiple discrete nanosheets (first plurality and second plurality) stacked vertically, with a gate electrode wrapping around each nanosheet. This segmentation enables independent control of multiple channels, improving current control capability while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The gate electrode is configured to surround each nanosheet in a nested manner, with the gate wrapping around the nanosheet channel. This nested configuration provides multi-gate control where the gate electrode envelops the channel from multiple sides, enhancing current control capability without proportionally increasing device complexity
2Reliability
If the gate length of multi-gate transistor is increased to improve current control, then current control capability is improved, but device area increases
Solution Approach 1:
The transistor structure transitions from a planar 2D channel to a vertical 3D stacked configuration with multiple nanosheets arranged in the vertical dimension. The gate electrode wraps around each nanosheet, providing control from multiple spatial directions. This dimensional change enables enhanced current control capability without increasing the lateral device footprint
3Reliability
If conventional multi-gate structure is used to suppress short channel effect, then short channel effect is reduced, but threshold voltage control flexibility is limited
Solution Approach 1:
Different nanosheets in the stacked structure can be selectively doped or configured with different properties. The first plurality of nanosheets and second plurality of nanosheets can have distinct characteristics, enabling local optimization of threshold voltage for different channel regions while collectively suppressing short channel effects through the multi-gate configuration
Solution Approach 2:
The threshold voltage can be controlled by changing parameters such as the doping concentration, material composition, or geometric dimensions of individual nanosheets. The multi-gate structure allows independent adjustment of these parameters for different nanosheets, providing flexible threshold voltage control while maintaining effective short channel effect suppression
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.