Upper Substrate Dummy Structures for POP Warpage Control

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Solution Overview

Problem

The warpage issues in package-on-package (POP) structures due to mismatched coefficients of thermal expansion (CTE) between lower and upper substrates in semiconductor packages, leading to reliability concerns.

Innovation Solution

Incorporating dummy structures with a lower CTE into the upper substrate to align its CTE with that of the lower substrate, thereby reducing the CTE difference and improving warpage characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an interposer substrate is used in a package-on-package structure, then electrical connection between upper and lower substrates is achieved, but warpage occurs due to significant differences in the coefficient of thermal expansion between substrates

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidsubstrate warpage
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent modifies the thermal expansion parameters of the upper substrate by integrating dummy structures with different CTE characteristics. This changes the overall thermal expansion behavior of the upper substrate to better match the lower substrate, thereby reducing warpage while maintaining electrical connection functionality

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The upper substrate is designed as a composite structure combining functional wiring layers with dummy structures. This composite approach allows the substrate to simultaneously provide electrical interconnection and thermal expansion compensation, resolving the contradiction between connection reliability and warpage control

Inventive Principle:
Principle #40Composite materials

2Shape

If dummy structures are added to the upper substrate to control thermal expansion, then warpage is reduced, but the device complexity increases

Engineering Contradiction:
Improvesubstrate warpage controlVSAvoidupper substrate structure complexity
Core Design Contradiction:
ShapeVSDevice complexity

Solution Approach 1:

The dummy structures serve multiple functions: they act as thermal expansion compensation elements, provide mechanical support, and can be integrated with existing substrate fabrication processes. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while achieving warpage control

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces warpage and enhances the reliability of semiconductor packages by adjusting the CTE of the upper substrate using dummy structures, ensuring better structural integrity.

Implementation Method 1

the coefficient of thermal expansion (CTE) between the lower and upper substrates

Methodology Applied
Scientific EffectCoefficient of thermal expansion: Thermal Expansion

Data Source

PatentUS12622302B2Semiconductor package including a lower substrate and an upper substrate
Publication Date: 2026.05.05 SAMSUNG ELECTRONICS CO LTD
  • US12622302B2 patent drawing
  • US12622302B2 patent drawing
  • US12622302B2 patent drawing

AI summary

A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the plurality of dummy structures are disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers the upper wiring layer and extends in the through-holes; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate.