USB Terminating Circuit for Stable Handshake Pulse Generation
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Solution Overview
Problem
General USB circuits face voltage instability and drift during the handshake mode due to switch transistors operating in the saturation region, which affects the generation of Chirp K and Chirp J signals for high-speed data transmission.
Innovation Solution
A USB circuit design incorporating a power circuit and a terminating circuit with first and second load circuits, which selectively receive and output differential signals to generate stable pulse and data signals, preventing transistors from bearing excessive current and maintaining linear operation during handshake mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a general terminating circuit uses switch transistors to receive differential signals, then the circuit can output pulse signals and data signals, but the switch transistors bear excessive current during handshake mode causing voltage instability and drift
Solution Approach 1:
The terminating circuit is segmented into multiple parallel load circuits (first load circuit, second load circuit, third load circuit) that share the current burden. Each load circuit handles a portion of the differential signal processing, preventing any single switch transistor from bearing excessive current during handshake mode, thus maintaining voltage stability.
Solution Approach 2:
Multiple load circuits are merged in parallel to collectively handle the differential signal reception. This merging distributes the current load across multiple transistors rather than concentrating it in a single transistor, resolving the current bearing capacity issue while maintaining reliable voltage output.
2Power
If switch transistors operate in saturation region due to high current, then the circuit can handle high current loads, but voltage drift occurs on Chirp K and Chirp J signals
Solution Approach 1:
The current handling capability is segmented across multiple parallel load circuits. Each transistor operates within its linear region by handling a fraction of the total current, preventing saturation while collectively maintaining the required current handling capability for high-speed data transmission.
Solution Approach 2:
The operating region of the switch transistors is changed from saturation region to linear region by redistributing the current load. This parameter change ensures precise voltage output for Chirp K and Chirp J signals while still accommodating the required current loads through parallel circuit configuration.
3Device complexity
If a single load circuit is used for differential signal reception, then the circuit structure is simple, but the circuit area and power consumption increase during handshake mode
Solution Approach 1:
The load circuits are configured to be dynamically selective - during handshake mode, multiple load circuits are activated to share the current load and reduce per-transistor stress; during normal data transmission mode, a single load circuit suffices. This dynamic configuration optimizes both circuit area utilization and power consumption based on operational requirements.
Solution Approach 2:
Each load circuit is designed with multi-functionality to handle both handshake mode operations and normal data transmission operations. The parallel configuration of multiple universal load circuits allows the system to adapt to different operational modes without requiring separate dedicated circuits, thereby managing circuit area efficiently.
Data Source
AI summary
A universal serial bus circuit including a power circuit and a terminating circuit is provided. The power circuit provides a differential signal. The terminating circuit is coupled to the power circuit. The terminating circuit receives the differential signal through the first signal output terminal and the second signal output terminal, and the terminating circuit includes a first load circuit and a second load circuit. When the universal serial bus circuit is operated in a handshake mode, the terminating circuit receives the differential signal through the first load circuit and the second load circuit, and outputs a pulse signal through the first signal output terminal and the second signal output terminal. When the universal serial bus circuit is operated in a normal mode, the terminating circuit receives the differential signal through the first load circuit, and outputs a data signal through the first signal output terminal and the second signal output terminal.