USB Sink FET Current Limiting for Inrush Damage Prevention
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Solution Overview
Problem
The existing USB-C specifications do not adequately address the risk of damaging field effect transistors (FETs) due to high inrush currents during power transitions, particularly when a power-sinking device switches from battery power to a USB-C charger, leading to potential thermal trips and component damage.
Innovation Solution
Implement a software algorithm in the embedded controller (EC) firmware to manage the timing and current limits of the sink FET, reducing the initial current limit after a power source connection, and gradually increasing it once the FET's input and output voltages equalize, thereby adhering to inrush current limits without requiring hardware changes or additional GPIO pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sink FET is enabled immediately upon USB-C charger connection to provide power to the system, then power delivery speed is improved, but high inrush currents cause thermal trips and potential FET damage
Solution Approach 1:
The system performs preliminary voltage equalization between the input and output sides of the sink FET before enabling it to carry full load current. This preliminary action prevents high inrush currents and thermal trips by ensuring the FET is properly biased and voltage-stabilized before full power delivery begins, thus protecting FET reliability while enabling fast power delivery.
2Reliability
If the initial current limit is reduced to prevent FET thermal trips, then FET damage is avoided, but power delivery speed decreases
Solution Approach 1:
The system dynamically adjusts the current limit of the sink FET based on the equalization progress between input and output voltages. Initially, a reduced current limit is applied to prevent thermal trips. As voltage equalization progresses and the FET becomes properly biased, the current limit is gradually increased to enable fast power delivery. This dynamic adjustment resolves the contradiction by adapting the current limit to the real-time state of the FET.
3Reliability
If a hardware circuit is added to monitor and control sink FET current limits, then FET protection is improved, but device complexity and cost increase
Solution Approach 1:
The system uses existing USB-C power delivery negotiation mechanisms and built-in FET control capabilities to monitor voltage equalization and adjust current limits. Rather than adding external hardware monitoring circuits, the embedded controller leverages the existing power management infrastructure to detect voltage conditions and regulate FET current, achieving FET protection without increasing device complexity or cost.
4Ease of operation
If additional GPIO pins are added to control FET timing and current limits, then power transition control is improved, but device complexity and cost increase
Solution Approach 1:
The system uses existing multi-functional control mechanisms within the USB-C power delivery protocol and embedded controller to manage FET timing and current limits. The same control logic that handles power negotiation and voltage regulation is extended to manage FET equalization, eliminating the need for dedicated GPIO pins. This universal approach improves power transition control while avoiding additional device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents FET damage by managing current limits based on system states, ensuring stable power transitions and reducing the risk of thermal shutdowns, while being cost-effective and compatible with existing USB-C deployments.
Implementation Method 1
a field effect transistor (FET) communicatively coupled with the USB-C port; identifying a power state of the system in response to the identification that the system has been coupled with the power source
Implementation Method 2
reducing the initial current limit after a power source connection, and gradually increasing it once the FET's input and output voltages equalize, thereby adhering to inrush current limits without requiring hardware changes
Data Source
AI summary
Embodiments herein relate to avoiding damage to a transistor in a power-sinking device that receives power from an external power source via a Universal Serial Bus port. In one aspect, a controller of the device sets a current limit to a reduced level during a wait period after the external power source is connected to the power-sinking device. The wait period avoids damage to the transistor by allowing its input and output voltages to equalize before the current is increased. Upon expiration of the wait period, the current limit is increased to a level negotiated with the external power source. Other aspects involve considering a sleep or low/dead battery state of the power-sinking device. The current limit can be set by programming a current limit of a battery charger coupled to between the transistor and a power bus of the device.