USB SOF Clock Synchronization for Stable Isochronous Transmission
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Solution Overview
Problem
USB isochronous data transmission between master and slave devices often experiences frequency differences due to system frequency oscillators operating at slightly different frequencies, leading to data instability and noise generation, with existing solutions like analog phase lock loops and controller firmware not fully addressing the issue.
Innovation Solution
A frequency synchronizing apparatus for the slave device that uses a Start of Frame (SOF) signal to generate a lock frequency signal, adjusting the frequency divider's variable frequency factor based on detected deviations to synchronize with the master device, employing a counter unit to calculate deviations and an adjusting unit to generate proportional adjusting values for continuous feedback control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog phase lock loop is used to synchronize frequencies, then frequency synchronization can be achieved, but the circuit complexity increases and manufacturing cost rises
Solution Approach 1:
The patent replaces the analog phase lock loop (hardware-based) with a digital frequency synchronization method implemented through firmware algorithms. The slave device uses a frequency counter and microcontroller to detect and adjust frequency deviations digitally, eliminating the need for complex analog circuits while achieving the same synchronization goal.
Solution Approach 2:
The patent changes the approach from analog signal processing to digital parameter measurement and adjustment. By using a frequency counter to measure the number of clock cycles within a reference period and adjusting the USB clock divider ratio based on detected deviations, the system achieves synchronization through parameter changes rather than analog circuit adjustments.
2Reliability
If controller firmware is used for frequency synchronization, then some improvement can be achieved, but the solution is not as effective as hardware modification and becomes complicated due to different controller specifications
Solution Approach 1:
The patent creates a universal frequency synchronization method that works across different controller manufacturers and specifications. By implementing the synchronization logic in firmware that independently measures frequency using a counter and reference clock, rather than relying on manufacturer-specific hardware features, the solution achieves broad compatibility while maintaining effectiveness.
3Manufacturing precision
If over-sampling ADC is used in the master device, then data transmission quality can be improved, but additional circuit matching requirements increase design difficulty and manufacturing cost
Solution Approach 1:
The patent implements a feedback mechanism where the slave device continuously monitors the frequency of the master device's USB clock using a counter, detects deviations from the expected frequency, and adjusts its own clock divider ratio to compensate. This feedback loop ensures that the sampling rate maintains the correct relationship with the master device's over-sampling clock, eliminating the need for additional matching circuits.
Data Source
AI summary
A universal series bus (USB) frequency synchronous apparatus using a start of frame (SOF) signal generated by a master device to mark a reference interval is disclosed. The frequency synchronizing apparatus includes a frequency divider, a counter unit with a default pulse number, an arithmetic unit, and an adjusting unit. The frequency divider divides a high frequency signal by a variable frequency factor to generate a lock frequency signal. The counter is used to detect a pulse number of the lock frequency signal at a reference interval and obtain a pulse difference between the default pulse number and the detected pulse number of the lock frequency signal.