Transfer Request Block Cache for USB Data Transfer Efficiency

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Solution Overview

Problem

Conventional USB systems experience time delays and increased power consumption due to repeated reading of transfer request blocks (TRBs) from system memory, which hampers data transfer efficiency.

Innovation Solution

A TRB cache system comprising a cache, a mapping table, and a cache controller that pre-fetches and stores TRBs, allowing direct retrieval from the cache instead of system memory, thereby reducing repeated reads and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the host reads TRBs from system memory in sequence, then the data transfer can proceed, but repeated reading of the same TRBs causes time delay and increases power consumption

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidtime delay due to repeated reading

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent implements a TRB cache that pre-loads and stores frequently accessed TRBs before they are needed by the host. The cache controller proactively fetches TRBs from system memory and stores them in the cache, so when the host needs to read TRBs, they are already available in the cache, eliminating repeated reading delays and improving data transfer efficiency

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the host repeatedly reads TRBs from system memory, then the system can handle device readiness variations, but this causes increased power consumption

Engineering Contradiction:

Improvehandling device readinessVSAvoidpower consumption during TRB reading

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent creates a copy of TRBs in the cache memory that mirrors the system memory content. Instead of repeatedly reading from system memory, the host reads from the cache copy, which requires minimal power. The cache controller maintains this copy and updates it as needed, ensuring reliability while dramatically reducing power consumption associated with repeated memory access operations

Inventive Principle:

Principle #26Copying

3Productivity

If the host reads TRBs from system memory each time, then the system maintains simplicity, but this results in time waste and reduced efficiency

Engineering Contradiction:

Improveproduction efficiencyVSAvoidtime waste from repeated reading operations

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a TRB cache as an intermediary layer between the host and system memory. The cache controller manages this intermediary structure, intercepting read requests from the host and serving TRBs from the cache when available. This intermediary mechanism eliminates the need for the host to directly access system memory repeatedly, thereby reducing time waste and improving production efficiency without complicating the host's operation

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8700859B2Transfer request block cache system and method

Publication Date: 2014.04.15 VIA TECH INC

AI summary

The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB addresses in a system memory. A cache controller pre-fetches the TRBs and stores them in the cache according to the content of the mapping table.