VNAND Channel Connection Layer Spacing for Defect Reduction
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Solution Overview
Problem
Conventional VNAND structures face defects when forming a common source line due to incomplete etching of the etch stop layer, leading to defects in channel connections.
Innovation Solution
A channel connection layer is patterned before forming the common source line, ensuring it is spaced apart from the common source line to reduce defect likelihood during its formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the etch stop layer is used to form the common source line, then the common source line can be formed, but incomplete etching occurs leading to defects in channel connections
Solution Approach 1:
The channel connection layer is formed and positioned in advance before the common source line formation process. This preliminary action ensures that the channel connection layer is already in place and properly spaced, preventing etching defects that would occur if the etch stop layer were used instead.
Solution Approach 2:
The channel connection layer serves as an intermediary structure between the first gate structure and the common source line. By using this intermediate layer with controlled spacing, the patent avoids the direct etching issues that occur when forming the common source line through the etch stop layer, thereby reducing defects.
2Reliability
If the channel connection layer is spaced apart from the separation regions, then defect likelihood is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The channel connection layer is given different spatial characteristics: it is spaced apart from separation regions to reduce defects, while simultaneously surrounding second channels to ensure proper electrical connection. This local differentiation of spacing requirements optimizes both reliability and manufacturability.
Solution Approach 2:
The spacing distance between the channel connection layer and separation regions is optimized to a specific range that balances defect reduction with manufacturing feasibility. By controlling this parameter within an appropriate range, the patent achieves both low defect rates and reasonable manufacturing precision requirements.
Data Source
AI summary
A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions.