Variable Bypass Clocking During PLL Re-Lock in P-State Transitions
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Solution Overview
Problem
Modern processors face performance degradation during P-state transitions due to the use of fixed bypass clocks, which are set lower than both the original and target frequencies, leading to inefficiencies in power and performance management, particularly in mobile and high-performance computing environments.
Innovation Solution
Implementing a variable frequency bypass clock that adjusts dynamically based on current and target P-states, using dither circuitry to smooth transitions and maintain higher frequencies during re-lock intervals, thereby reducing performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed bypass clock is used during PLL re-lock interval, then the system maintains stable operation during P-state transitions, but the processor performance degrades due to lower clock frequency
Solution Approach 1:
The bypass clock frequency is changed from a fixed value to a variable value that dynamically adjusts based on the current and target P-state frequencies. The bypass clock selector selectively provides different bypass clock frequencies corresponding to different P-state transitions, ensuring the bypass clock frequency is optimized for each specific transition scenario rather than using a single conservative frequency for all transitions.
Solution Approach 2:
The key parameter changed is the bypass clock frequency. Instead of using a fixed bypass clock frequency that is lower than both original and target P-state frequencies, the system changes the bypass clock frequency parameter to be closer to or equal to the target P-state frequency based on the specific transition, thereby improving performance during re-lock intervals while maintaining stability.
2Object-affected harmful factors
If a lower frequency bypass clock is used during re-lock interval, then potential damage during peak current scenarios is prevented, but performance is substantially reduced
Solution Approach 1:
The bypass clock frequency parameter is dynamically adjusted based on the specific P-state transition context. Instead of always using a conservatively low frequency to prevent peak current damage, the system selects bypass clock frequencies that are optimized for each transition scenario, allowing higher frequencies when safe and improving overall performance while still providing protection when needed.
Solution Approach 2:
The bypass clock system transitions from a static, one-size-fits-all frequency approach to a dynamic, context-aware frequency selection mechanism. The bypass clock selector dynamically chooses appropriate frequencies based on current and target P-states, enabling the system to adapt to different operational conditions and avoid unnecessary performance degradation.
Data Source
AI summary
Techniques are disclosed for managing clock signals during transitions between performance states (P-states) in processors. In some embodiments, an apparatus includes processor circuitry configured to operate based on an input clock signal at different input clock frequencies in different performance states. Phase-locked loop (PLL) circuitry provides the input clock signal at the different input clock frequencies. Bypass circuitry provides a bypass clock signal during different re-lock intervals in which the PLL circuitry adjusts the frequency of the input clock signal for a change from a first performance state to a second performance state. The bypass circuitry is configured to provide the bypass clock signal at a first frequency during a first re-lock interval and at a second, different frequency during a second re-lock interval. Dither circuitry may dither the bypass clock signal during the re-lock intervals, based on factors such as the origin and target performance states.