Semiconductor Gate Structure With Variable Capping Thickness
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Solution Overview
Problem
Current semiconductor devices face challenges in improving element performance and reliability, particularly in scaling technologies for increasing density and suppressing short channel effects in multi-gate transistors.
Innovation Solution
The semiconductor device incorporates a unique structure with a lower pattern and sheet patterns on a substrate, featuring different thicknesses of capping patterns under gate structures, and includes inner gate structures between sheet patterns, utilizing (110) crystal planes for enhanced channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi gate transistor with three-dimensional channel is used for scaling, then device density is increased, but short channel effects are not effectively suppressed
Solution Approach 1:
The channel region is segmented into multiple discrete sheet patterns (first sheet pattern, second sheet pattern, etc.) spaced apart from each other, rather than forming a continuous three-dimensional channel. This segmentation allows independent control of each sheet pattern's electrical characteristics and enables better suppression of short channel effects while maintaining high device density through the multi-pattern structure.
Solution Approach 2:
Different gate structures (first gate structure, second gate structure, etc.) are positioned to control different sheet patterns locally. The gate insulating film thickness is varied in different regions (thinner under first gate structure, thicker under second gate structure) to optimize current control for each local region, enabling simultaneous scaling and effective short channel effect suppression.
2Productivity
If gate length is not increased to maintain scaling, then device density is preserved, but current control capability deteriorates
Solution Approach 1:
The gate control is extended into the vertical dimension by forming gate structures that extend over multiple sheet patterns in the thickness direction. The gate insulating film is configured with different thicknesses at different vertical positions, enabling three-dimensional current control that compensates for reduced gate length while maintaining high device density.
Solution Approach 2:
The gate insulating film thickness parameter is varied spatially (thinner under first gate structure, thicker under second gate structure) to optimize the electrical characteristics of each region. This parameter change enables enhanced current control capability without increasing gate length, preserving device density through the optimized thickness profile.
3Ease of manufacture
If uniform capping pattern thickness is used, then manufacturing is simplified, but element performance is limited
Solution Approach 1:
The capping pattern is designed with non-uniform thickness (first capping thickness under first gate structure, second capping thickness under second gate structure) to locally optimize the electrical properties of each region. This local quality variation enhances element performance by enabling independent optimization of each gate structure's performance characteristics while remaining manufacturable through standard epitaxial growth processes.
Data Source
AI summary
There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.