Variable Clock Gating Hysteresis for Power and Noise Reduction
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Solution Overview
Problem
In electronic systems, particularly in portable devices, clock signals consume significant power and generate signal noise, leading to increased power consumption and interference, which existing clock control techniques have not adequately addressed.
Innovation Solution
A clock signal generation circuit that varies the gating hysteresis of clock signals based on attributes of communications transactions, such as addresses or payloads, and a control circuit that stores and selects time delays to optimize clock gating, reducing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are continuously generated to ensure data processing operations, then processing speed and reliability are maintained, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal is selectively enabled or disabled based on real-time detection of data processing activity. The system transitions from static continuous clock generation to dynamic conditional generation, adjusting clock signal presence according to actual processing needs rather than operating at fixed state
Solution Approach 2:
The system employs feedback mechanisms by monitoring data processing operations and using this information to control clock signal generation. The detection of processing activity feeds back to the clock gating logic, creating a closed-loop control system that automatically adjusts clock signal presence based on actual system state and processing requirements
2Productivity
If clock signals are generated at high frequency to improve data processing speed, then processing throughput increases, but signal noise increases and interferes with adjacent operations
Solution Approach 1:
The patent implements periodic clock signal generation rather than continuous generation, enabling clocks only during actual data processing intervals. This periodic activation pattern reduces overall signal noise exposure while maintaining high-frequency operation during active periods, thus preserving processing throughput when needed while minimizing harmful electromagnetic interference during idle periods
3Use of energy by moving object
If clock gating is implemented to reduce power consumption, then energy efficiency improves, but latency increases due to clock signal re-enablement delays
Solution Approach 1:
The patent applies preliminary action by providing hysteresis delay in the clock gating logic that keeps the clock signal enabled for a predetermined period after processing activity ceases. This anticipates potential reactivation needs and maintains clock signal presence longer than strictly necessary, thereby reducing re-enablement latency when new processing operations begin while still achieving significant power savings during extended idle periods
Data Source
AI summary
An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.