Variable Delay Circuit for Glitch-Free Real-Time Timing Adjustment
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Solution Overview
Problem
Existing delay circuits in SoCs are either fixed, leading to variations with PVT changes, or adjustable but prone to introducing glitches when delay time is adjusted, limiting adjustments to signal inactivity to prevent glitches.
Innovation Solution
A variable delay circuit system comprising multiple delay units and circuitry that adjusts control signals based on the outputs of these units to change delay times without causing glitches, allowing adjustments even when the signal is active.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay time is made adjustable in a delay circuit, then adaptability to different timing requirements is improved, but glitches are introduced to the signal being delayed
Solution Approach 1:
The delay circuit is divided into multiple delay units, each providing a specific delay amount. By selectively enabling or disabling individual delay units, the total delay time is adjusted in discrete steps without causing glitches to the delayed signal.
Solution Approach 2:
The delay circuit dynamically adjusts its total delay time by selectively activating or deactivating specific delay units based on control signals, allowing real-time adaptation of delay parameters while maintaining signal integrity.
2Productivity
If delay time is adjusted when signal is active, then productivity is improved, but glitches are introduced to the signal
Solution Approach 1:
The delay path is segmented into multiple independent delay units that can be selectively enabled or disabled. This segmentation allows the circuit to adjust total delay time by switching between combinations of delay units without interrupting the signal flow, enabling delay adjustment during active signal periods without introducing glitches.
Solution Approach 2:
Control circuitry acts as an intermediary that manages the selection and activation of individual delay units. This control mechanism coordinates the switching between different delay configurations, ensuring smooth transitions that maintain signal integrity even during active signal periods.
Data Source
AI summary
An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.