Variable Delay Circuit for Wide-Range VCO Frequency Tuning
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Solution Overview
Problem
Existing multi-band voltage-controlled oscillator (VCO) circuits face challenges in scaling with semiconductor fabrication processes due to poor process portability and voltage scalability, and limited tuning range, especially with techniques like switched biasing currents and capacitive or inductive tuning.
Innovation Solution
A variable delay circuit architecture using transistors that can be discretely enabled or disabled to adjust pull-up or pull-down current paths, allowing for wide frequency range coverage with high frequency resolution and minimal area penalty, and easy portability across different semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If switched biasing currents or capacitive/inductive tuning is used to achieve wide frequency range, then frequency tuning range is improved, but process portability and voltage scalability deteriorate
Solution Approach 1:
The patent changes the fundamental parameter used for frequency tuning from biasing currents or external capacitors/inductors to the intrinsic gate capacitances of the transistors themselves. By varying the gate capacitance values (Cgs, Cgd) through transistor sizing and configuration, the VCO achieves wide frequency tuning range while maintaining excellent process portability, as the tuning is now based on parameters that scale naturally with the fabrication process.
Solution Approach 2:
The transistor's own parasitic capacitances (gate-to-source and gate-to-drain capacitances) are utilized as the tuning mechanism instead of requiring external passive components. This self-service approach eliminates the need for large external capacitors or inductors, improving both process portability and integration while achieving the desired frequency range.
2Adaptability or versatility
If switched biasing currents or capacitive/inductive tuning is used to achieve wide frequency range, then frequency tuning range is improved, but voltage scalability deteriorates
Solution Approach 1:
The patent transitions from current-based tuning (which requires sufficient voltage headroom for biasing) to capacitance-based tuning using gate capacitances. This parameter change enables voltage scalability because the gate capacitance tuning mechanism does not depend on maintaining specific voltage levels for biasing currents, allowing the VCO to operate effectively across different voltage scales.
3Adaptability or versatility
If traditional tuning techniques are used, then frequency range is improved, but area usage increases
Solution Approach 1:
The patent exploits the intrinsic gate capacitances of the transistors that are already present in the circuit for switching and amplification functions. By repurposing these existing parasitic elements for frequency tuning, the design achieves wide tuning range without adding separate large-value capacitors or inductors, thereby minimizing the additional area required.
Solution Approach 2:
The transistors in the VCO serve multiple functions: they provide the amplification needed for oscillation, the switching for frequency selection, and simultaneously provide the gate capacitances for frequency tuning. This multi-functionality eliminates the need for dedicated tuning components, reducing overall circuit area while maintaining wide frequency range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables a VCO to achieve a wide tuning range with high frequency resolution and minimal area usage, while being easily portable across different semiconductor fabrication processes, overcoming the limitations of existing techniques.
Implementation Method 1
The delay of the inverting delay circuit may be controlled by a gate capacitance of the transistors, such as a gate-to-source capacitance (Cgs) or a gate-to-drain capacitance (Cgd)
Data Source
AI summary
A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.