Variable-Input ECC Circuits Using Filler Bits Across Memory Modes
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accommodating different numbers of bits accessed during operations without altering the logic tree of the ECC circuit, as they operate in various modes with varying input bit requirements.
Innovation Solution
The implementation of an ECC input circuit that generates filler bits to ensure a consistent number of input bits for the ECC engine, regardless of the operational mode, by adding logical filler bits or patterned filler bits to match the expected input requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ECC circuit is designed with a fixed logic tree for a specific number of input bits, then the error correction functionality is reliable and precise, but the device cannot accommodate different operational modes with varying bit access requirements
Solution Approach 1:
The patent applies dynamics by making the ECC circuit configurable through select signals that dynamically adjust the logic tree configuration. The select signals enable or disable specific logic gates and pathways, allowing the same physical circuit to adapt its structure based on operational mode requirements without requiring multiple fixed circuits
Solution Approach 2:
The patent implements universality by designing a single ECC circuit that can handle multiple operational modes (e.g., 512-bit, 256-bit, 128-bit modes) through reconfiguration. The same logic tree infrastructure serves multiple functions by selectively activating different portions of the circuit based on the required bit width, eliminating the need for separate dedicated circuits for each mode
2Adaptability or versatility
If the ECC circuit is reconfigured for each operational mode, then the device can handle variable bit access, but the logic tree structure must be altered which increases complexity
Solution Approach 1:
The patent applies preliminary action by pre-configuring the logic tree with all possible pathways and gates, controlled by select signals that are set before operation begins. The circuit is designed with redundant logic elements that are selectively activated or deactivated based on the operational mode, rather than physically reconfiguring the structure during operation
Solution Approach 2:
The patent changes parameters by using select signals to modify the effective number of active input bits and logic gate configurations. By changing the state of select signals, the circuit transitions between different operational configurations (e.g., from 512-bit to 256-bit mode) without physical structural changes, only logical activation patterns
3Reliability
If filler bits are added to match expected input requirements, then consistent input bit counts are maintained for the ECC engine, but additional circuit logic is required to generate and manage these filler bits
Solution Approach 1:
The patent uses an intermediary approach by introducing select signals as mediators between the variable input data and the fixed-structure ECC engine. These select signals coordinate the activation of filler bit generation pathways and control which data bits are routed to the ECC logic, ensuring the engine receives a consistent number of valid input bits regardless of the operational mode
Solution Approach 2:
The patent treats filler bits as disposable elements that are generated temporarily to pad variable-length data to the required fixed length for ECC processing. These filler bits serve their purpose of maintaining consistent input width and are then discarded or ignored in the final output, requiring minimal permanent storage or complex management infrastructure
Data Source
AI summary
Apparatuses, systems, and methods for variable input error correction code (ECC) circuits. Different modes of a memory device may involve different numbers of bits of information (e.g., data and/or metadata) being accessed. An ECC input circuit receives the variable number of bits of information and provides a fixed number of input bits. An ECC engine uses the input bits to generate parity (during a write) or to locate errors (during a read). The number of input bits may be based on a number of inputs of the ECC engine. The ECC input circuit may generate filler bits to add to the bits of information to generate the input bits.