Variable Interval Column Portions in 3D Memory Arrays

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Solution Overview

Problem

In three-dimensional memory cell arrays, the narrow intervals between memory holes lead to deteriorated embeddability of metal films, resulting in voids between memory holes and metal films, increasing defective memory cells during the replacement process of insulation films with metal films.

Innovation Solution

The semiconductor device design includes varying intervals between column portions in the memory cell array, increasing the distance from the slit ST, which improves the embeddability of electrode films by ensuring sufficient embedding of conductive metal into deep portions, reducing void formation and enhancing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the interval between adjacent memory holes is narrowed to increase memory hole density, then the density of memory holes is improved, but the embeddability of metal films deteriorates and voids form between memory holes and metal films

Engineering Contradiction:
Improvedensity of memory holesVSAvoidembeddability of metal films
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the interval between column portions variable rather than uniform. Specifically, the interval is set to be larger in regions closer to slits and smaller in regions farther from slits. This local variation in spacing allows metal films to be properly embedded near slits (where space is more constrained) while maintaining high density in other regions, thus resolving the contradiction between overall density and local embeddability.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the interval between adjacent memory holes is narrowed to increase memory hole density, then the density of memory holes is improved, but voids remain between memory holes and metal films increasing defective memory cells

Engineering Contradiction:
Improvedensity of memory holesVSAvoidyield of memory cells
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements local quality by creating non-uniform intervals between column portions based on their position relative to slits. By setting larger intervals near slits and smaller intervals farther from slits, the design ensures reliable metal film embedding and void-free structures in critical areas while maximizing overall memory hole density. This positional differentiation maintains high yield without sacrificing density.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If uniform small intervals are used between column portions to maximize density, then the density is improved, but the embeddability of electrode films deteriorates

Engineering Contradiction:
Improvedensity of column portionsVSAvoidembeddability of electrode films
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent applies local quality by making the interval between column portions position-dependent. Intervals are set to be larger in regions closer to slits where embedding is more difficult, and smaller in regions farther from slits where embedding is easier. This local differentiation optimizes both manufacturability (by ensuring proper embedding where needed) and density (by minimizing intervals where possible).

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of interval size from a uniform constant to a variable parameter that depends on position relative to slits. By adjusting the interval parameter locally based on spatial coordinates, the design achieves optimal balance between embeddability and density without requiring a uniform compromise across the entire structure.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230225122A1Semiconductor device
Publication Date: 2023.07.13 KIOXIA CORP
  • US20230225122A1 patent drawing
  • US20230225122A1 patent drawing
  • US20230225122A1 patent drawing

AI summary

A semiconductor device includes a stack including first electrode films stacked in a first direction. First and second isolating portions isolate the first electrode films. Third and fourth isolating portions isolate only one or more of the first electrode films in an upper portion of the first electrode films in the stack in a third direction, and are arranged in the third direction between the first and second isolating portions. The column portions include first and second column portions between the first and third isolating portions. The column portions include third and fourth column portions between the third and fourth isolating portions. The second column portion is adjacent to the first column portion. The fourth column portion is adjacent to the third column portion. A first interval between the first and second column portions is different from a second interval between the third and fourth column portions.