Variable Period Clock Signal for Hardware Verification
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Solution Overview
Problem
Conventional hardware emulation systems are inefficient as they use a fixed number of system clock cycles for every design cycle, regardless of propagation delays, leading to prolonged verification times due to unnecessary slowdowns when no change occurs in derived clock signals.
Innovation Solution
A hardware verification system generates a variable period clock signal with different periods based on propagation delays, applying a shorter period when no change is expected and a longer period when a change is anticipated, thereby adapting to the specific signal paths and reducing overall verification time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a fixed number of system clock cycles is used for every design cycle, then the emulation system maintains simplicity in clock management, but the verification time is prolonged due to unnecessary slowdowns when no change occurs in derived clock signals
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed clock period to a variable clock period that adapts based on signal change detection. The emulation system dynamically adjusts the number of system clock cycles allocated to each design cycle based on whether derived clock signals have changed, thereby optimizing verification time without excessive complexity
Solution Approach 2:
The patent changes the parameter of clock period from a constant value to a variable value. The system monitors derived clock signals and adjusts the clock period parameter accordingly - using a shorter period when no change is detected and a longer period when changes are anticipated, directly addressing the verification time issue
2Productivity
If the system waits for the same number of system clock cycles for every design cycle, then the clock management is straightforward, but the emulation speed is reduced when changes occur infrequently
Solution Approach 1:
The patent implements feedback by continuously monitoring derived clock signals to detect changes. This feedback mechanism informs the clock management system whether to use a shorter or longer clock period for the next design cycle, thereby maintaining high emulation speed when appropriate while ensuring correctness when changes occur
Solution Approach 2:
The system performs preliminary detection of signal changes before committing to a clock period. By monitoring derived clock signals in advance and predicting whether changes will occur, the system can proactively select the optimal clock period, improving emulation speed without sacrificing accuracy
Data Source
AI summary
A hardware verification system includes, in part, a multitude of programmable devices and a system clock. The hardware verification system receives a circuit design and generates a variable period clock from the system clock by analyzing propagation delays in different signal paths of the circuit design. The variable period clock has a first period that occurs in each N cycles of the system clock and a second period that occurs in each M cycles of the system clock, in which M>N. The variable period clock is applied to at least one of the programmable devices to verify the circuit design.