Variable Resistance Memory Bit Line Control
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Solution Overview
Problem
Semiconductor memory devices with cross-point array structures using phase changeable materials face failures due to peak currents when writing data, particularly affecting adjacent memory cells.
Innovation Solution
A variably resistive memory device with a memory cell array and control circuit block, including bit line and word line control circuits, which selectively apply voltages and currents based on the location of memory cells to manage and reduce peak currents by using high, middle, and low resistance networks in series, and controlling the driving force of row switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a writing current is applied to the semiconductor memory device to store data, then data storage is achieved, but a fail is generated in an adjacent cell due to peak current
Solution Approach 1:
The patent applies different resistance values to different bit line segments based on their location. Adjacent cells near the control circuit block are connected through high resistance networks, middle cells through middle resistance networks, and remote cells through low resistance networks. This local differentiation allows the writing current to be appropriately limited for adjacent cells while maintaining sufficient current for remote cells, thereby preventing peak current damage to adjacent cells during data storage operations
Solution Approach 2:
The patent changes the resistance parameter of the bit line networks based on cell location. By configuring high resistance networks for adjacent cells, middle resistance networks for middle cells, and low resistance networks for remote cells, the patent dynamically adjusts the current characteristics to different spatial zones. This parameter change approach ensures that adjacent cells receive limited current during write operations, preventing peak current failures while maintaining data storage functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces peak currents and stabilizes voltages during write operations, preventing failures and ensuring reliable data storage in adjacent, middle, and remote cell groups.
Implementation Method 1
a phase changeable layer including a memory layer configured to change phase between a crystalline state and an amorphous state
Implementation Method 2
when a writing current is applied to the semiconductor memory device to store data
Data Source
AI summary
A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.