Variable Resistance Memory Device Using Carbon Nanotubes
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and reliability due to limitations in fine pattern forming technology and the high cost of required equipment.
Innovation Solution
A variable resistance memory device is designed with a stack of insulating and conductive sheets alternatingly stacked on a substrate, featuring a vertical hole and a conductive pattern extending vertically, with a resistance varying layer composed of carbon nanotubes between the conductive pattern and the stack's inner side surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited due to area constraints and fine pattern forming requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction, with conductive sheets and insulating sheets forming a three-dimensional structure. This dimensional change allows significantly higher integration density without requiring extremely fine pattern forming technology, as the stacking approach utilizes the vertical dimension rather than relying solely on planar miniaturization.
2Productivity
If three-dimensionally arranged memory cells are used, then integration density is increased, but manufacturing complexity and equipment cost increase
Solution Approach 1:
The memory device is segmented into multiple discrete layers including conductive sheets, insulating sheets, and resistance changing layers, which are stacked vertically. Each layer can be formed and processed relatively independently, allowing for modular manufacturing. The segmented structure enables complex three-dimensional functionality to be achieved through sequential layer deposition and processing steps, rather than requiring extremely complex single-step processes.
Solution Approach 2:
The patent employs composite material structures combining organic and inorganic materials, such as carbon nanotubes with metal electrodes, or phase-change materials with surrounding structural layers. These composite structures enable the realization of three-dimensional memory cells with enhanced functionality while managing the manufacturing complexity through material property optimization rather than purely geometric complexity.
3Ease of manufacture
If conventional resistance varying layers are used, then manufacturing is easier, but reliability and localized resistance control are insufficient
Solution Approach 1:
The resistance varying layer is designed with spatially varying properties, including regions with different resistance values, thickness variations, and localized material composition changes. This allows different portions of the memory cell to have optimized resistance characteristics tailored to specific functional requirements, improving overall device reliability and enabling localized control of electrical properties without compromising manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration density and reliability by allowing for localized control of resistance in the memory device, improving data writing operations and maintaining electric reliability.
Implementation Method 1
The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets and a second carbon nanotube electrically connected to the conductive pattern.
Data Source
AI summary
A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.