Variable Resistance Memory Device with Dielectric Fill
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Next-generation semiconductor memory devices face challenges in improving electrical characteristics and simplifying the fabrication process while maintaining resistance changes based on applied electric current or voltage, and ensuring data retention without power supply interruption.
Innovation Solution
A variable resistance memory device is designed with a two-dimensionally arranged structure comprising conductive lines, memory cells with switching elements and variable resistance structures, and dielectric layers, where the first dielectric layer fills spaces between switching elements and top electrodes, and a second dielectric layer with a higher dielectric constant is used between top electrodes, facilitating a flowable vapor deposition and curing process for improved fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used for variable resistance memory devices, then manufacturing complexity is high, but electrical characteristics and process simplification are not achieved
Solution Approach 1:
The fabrication process is divided into distinct sequential steps: forming variable resistance structures, forming upper structures with switching elements and top electrodes, and forming dielectric layers. This segmentation allows each step to be optimized independently and simplifies the overall manufacturing process by breaking down complexity into manageable segments.
Solution Approach 2:
The variable resistance structures are formed first on the substrate before any other components are added. This preliminary action establishes the foundation for subsequent fabrication steps and allows for better control over the final device characteristics, simplifying the overall manufacturing process.
2Object-affected harmful factors
If dielectric layers are formed between memory cells, then cross-talk between cells is reduced, but fabrication process becomes more complex
Solution Approach 1:
The first dielectric layer filling the space between switching elements and the second dielectric layer filling the space between top electrodes are formed in a combined sequence. This merging of dielectric layer formation steps reduces the total number of separate fabrication processes while still providing effective isolation between memory cells, thereby reducing cross-talk without significantly increasing fabrication complexity.
Solution Approach 2:
The dielectric constant of the second dielectric layer is specifically increased compared to the first dielectric layer. This parameter change optimizes the electrical isolation between top electrodes while maintaining a relatively simple fabrication process, as the different dielectric constants can be achieved through material selection rather than complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances electrical characteristics and simplifies the fabrication process, reducing cross-talk and voids between memory cells, while maintaining resistance changes and ensuring data retention without power supply interruption.
Implementation Method 1
performing a flowable vapor deposition process to form a preliminary dielectric layer between the upper structures
Implementation Method 2
performing a curing process to cure the preliminary dielectric layer
Implementation Method 3
a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode
Data Source
AI summary
A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.