Variable Resistance Memory with Dual Dielectric Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory circuits face challenges in miniaturization, low power consumption, and high performance due to limitations in variable resistance element characteristics, particularly in semiconductor memory devices used in electronic devices.
Innovation Solution
The implementation of semiconductor memory devices with a variable resistance layer, a substituted dielectric layer, and an unsubstituted dielectric layer, where the unsubstituted layer has a higher porosity and lower thermal conductivity, is used to enhance the characteristics of memory cells, including the use of Si—N bonds and Si—H bonds, and materials like silazane, to improve data storage and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional dielectric layer is used in memory cells, then the structure is simple, but thermal disturbances affect the variable resistance layer and degrade memory characteristics
Solution Approach 1:
The dielectric layer is segmented into two distinct layers: a first dielectric layer with lower porosity and a second dielectric layer with higher porosity. This segmentation allows each layer to perform its specific function - the first layer provides structural support while the second layer offers thermal isolation, thereby improving memory characteristics without excessive complexity
Solution Approach 2:
Different regions of the dielectric structure are assigned different properties. The first dielectric layer has lower porosity for mechanical stability, while the second dielectric layer has higher porosity for thermal isolation. This local differentiation of properties optimizes both structural integrity and thermal management
2Reliability
If thermal isolation is enhanced to prevent thermal disturbances, then memory characteristics improve, but the device structure becomes more complex
Solution Approach 1:
The second dielectric layer is designed with higher porosity to provide superior thermal isolation properties. The porous structure reduces thermal conductivity, preventing thermal disturbances from affecting the variable resistance layer, thereby improving memory characteristics through material selection rather than complex configuration
3Productivity
If memory cells are miniaturized to improve device integration, then productivity increases, but variable resistance element characteristics deteriorate
Solution Approach 1:
As memory cells are miniaturized, the dual dielectric layer structure provides localized thermal management. The second dielectric layer with higher porosity is positioned adjacent to the variable resistance layer to provide targeted thermal isolation, ensuring that variable resistance characteristics are maintained even in miniaturized devices with higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the data storage characteristics and operating performance of memory devices by preventing thermal disturbances and enhancing the variable resistance properties of memory cells, leading to better performance and reliability in electronic devices.
Implementation Method 1
an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material
Implementation Method 2
a substituted dielectric layer filling a space between the plurality of memory cells
Data Source
AI summary
An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.