Variable Resistance Memory Device Etching Segmentation
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Solution Overview
Problem
During the manufacturing of variable resistance memory devices with a cross-point array structure, the selection layer and variable resistance layer are often damaged due to the etching process, leading to reliability issues.
Innovation Solution
The method involves forming conductive lines and memory units with a specific orientation, allowing for independent etching of the selection and variable resistance patterns using different etching masks, thereby reducing damage and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the selection layer and variable resistance layer are etched by the same etching process, then the manufacturing process is simplified, but the selection pattern and variable resistance pattern are damaged
Solution Approach 1:
The patent divides the etching process into two separate steps: first etching the selection layer to form the selection pattern, then etching the variable resistance layer to form the variable resistance pattern. This segmentation allows each layer to be etched with optimized parameters, preventing damage to the patterns while maintaining manufacturing feasibility.
Solution Approach 2:
The selection pattern is formed in advance before the variable resistance pattern is created. This preliminary action ensures that the selection pattern is already in place and protected when the variable resistance layer is subsequently etched, preventing damage to both patterns during the manufacturing process.
2Productivity
If the selection pattern and variable resistance pattern are formed simultaneously, then the manufacturing process is more efficient, but both patterns may be damaged
Solution Approach 1:
The patent segments the pattern formation into two distinct etching steps rather than attempting simultaneous formation. This allows each pattern to be created with precise control over etching parameters, ensuring high manufacturing precision while maintaining reasonable productivity through a systematic two-step process.
Solution Approach 2:
The selection pattern is formed as a preliminary step before creating the variable resistance pattern. This sequential approach ensures that each pattern is formed with optimal precision while the previously formed pattern serves as a reference structure, maintaining both high quality and manufacturing efficiency.
3Reliability
If different etching processes are used for the selection layer and variable resistance layer, then pattern damage is minimized, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the etching process into two separate steps with different etching conditions optimized for each layer. This segmentation enables the use of different etching processes for the selection layer and variable resistance layer, minimizing pattern damage while managing complexity through a systematic approach.
Solution Approach 2:
The patent applies different etching processes locally to different layers based on their specific requirements. The selection layer receives one type of etching treatment while the variable resistance layer receives another, allowing each layer to be processed with the most appropriate method for its material properties and pattern requirements.
Data Source
AI summary
A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.