Variable Resistance Memory Devices With Insulating Patterns

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Next-generation semiconductor memory devices require improved electrical characteristics, particularly in variable resistance memory devices, to enhance performance and reliability, which existing technologies have not adequately addressed.

Innovation Solution

The development of a variable resistance memory device with a specific structure involving multiple conductive lines, insulating patterns, and sub-insulating patterns, including air gaps, to optimize electrical performance and fabrication methods that involve forming recessed regions and etching processes to create these structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional memory device structure is used, then the device complexity is low, but the electrical characteristics and performance are insufficient

Engineering Contradiction:

Improveelectrical characteristicsVSAvoiddevice structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory device is divided into multiple functional layers including first and second insulating patterns, sub-insulating patterns, and multiple conductive lines. Each layer serves a specific function in maintaining electrical characteristics, with the insulating patterns providing isolation and the conductive lines enabling signal transmission, thereby improving overall device reliability through functional segmentation

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a nested structure where the sub-insulating pattern is positioned between the first and second insulating patterns, creating a multi-layered insulation system. This nested arrangement of insulating and conductive elements allows for improved electrical characteristics while maintaining a compact vertical structure

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If power supply is interrupted, then energy consumption is reduced, but data storage is lost in conventional devices

Engineering Contradiction:

Improvedata retentionVSAvoidpower supply dependency

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent utilizes materials with variable resistance characteristics that can maintain their resistance state (high or low resistance) even when power is interrupted. This parameter change in resistance allows the device to retain stored data without continuous power supply, improving reliability while reducing power dependency for data retention

Inventive Principle:

Principle #35Parameter changes

3Reliability

If existing fabrication methods are used, then manufacturing process is simple, but electrical performance is insufficient

Engineering Contradiction:

Improveelectrical performanceVSAvoidfabrication process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The fabrication process includes preliminary formation of insulating patterns and conductive lines before final memory cell assembly. The insulating patterns are pre-formed with specific geometries to ensure proper electrical isolation, and conductive lines are preliminarily structured to achieve optimal electrical performance in the final device

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11127900B2Variable resistance memory devices, and methods of forming variable resistance memory devices

Publication Date: 2021.09.21 SAMSUNG ELECTRONICS CO LTD

AI summary

Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.